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1. 发明申请

WO2015192095A1 CIRCUIT SKEW COMPENSATION TRIGGER SYSTEM 审中-公开
标题翻译：电路补偿触发系统
公开(公告)号：WO2015192095A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/035687
申请日：2015-06-12
申请人： SYNOPSYS, INC.
发明人： KAWA, Jamil , NGUYEN, Thu , LEUNG, Raymond
IPC分类号： H03K3/2893 , H03K5/1252
CPC分类号： H03K19/00384 , G11C5/14 , G11C8/08 , G11C11/417 , G11C29/023 , G11C29/028
摘要： A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.
摘要翻译：电路偏移补偿触发系统包括分压器，该分压器包括P晶体管和N晶体管，分压器中的中心节点拉至第一电平。电路偏移补偿触发系统还包括当P晶体管和N晶体管之间的偏斜高于阈值时激活的触发器。启动补偿器的触发器调整偏差。

2. 发明申请

WO2015176295A1 FEED-FORWARD BIAS CIRCUIT 审中-公开
标题翻译：进给前进偏置电路
公开(公告)号：WO2015176295A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078223
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit.In some aspects,the feed- forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.In some implementations,the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过使能产生不同偏置来补偿电路中的晶体管工艺角在一些实施方案中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

3. 发明申请

WO2013110019A1 TRANSITION TIME LOCK LOOP WITH REFERENCE ON REQUEST 审中-公开
标题翻译：过渡时间锁定环，请参考
公开(公告)号：WO2013110019A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/022344
申请日：2013-01-20
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wilson J. , TAN, Chiew-Guan
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00384
摘要： Output driver feedback circuitry limits output slew rates across a wide range of output loads. A transition time lock loop architecture of the feedback circuitry compares a transition time pulse with a reference pulse to adjusts transition time of an output signal for various process-voltage-temperature (PVT) process corners, output voltage domains and output capacitances. Reference pulse generation circuitry provides a reference pulse in phase with the transition time pulse for each rise and fall of the output signal.
摘要翻译：输出驱动器反馈电路可在多种输出负载范围内限制输出转换速率。反馈电路的转换时间锁定环结构将转换时间脉冲与参考脉冲进行比较，以调整各种过程电压 - 温度（PVT）过程角，输出电压域和输出电容的输出信号的转换时间。参考脉冲发生电路为输出信号的每个上升和下降提供与转换时间脉冲同相的参考脉冲。

4. 发明申请

WO2007105170A3 ELECTRONIC DEVICE AND INTEGRATED CIRCUIT 审中-公开
标题翻译：电子设备和集成电路
公开(公告)号：WO2007105170A3
公开(公告)日：2007-12-13
申请号：PCT/IB2007050848
申请日：2007-03-13
申请人： KONINKL PHILIPS ELECTRONICS NV , CHANDRA SUNIL
发明人： CHANDRA SUNIL
IPC分类号： H03K19/003
CPC分类号： H03K19/00384 , H03K19/00315 , H03K19/00361
摘要： An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (Pl, P2) and a first and second NMOS transistor (Nl, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3, P4) and a third and fourth NMOS transistor (N3, N4). The second driver circuit (20) is complementary to the first driver circuit (10) and switches in the opposite direction to the first driver circuit (10). A gate of the second and fourth PMOS transistor (P2, P4) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N2, N4) is coupled to a second bias voltage (REFn). A first capacitance (C3) is coupled between the gate and the drain of the fourth PMOS transistor (P4) and a second capacitance (C4) is coupled between the gate and the drain source of the fourth NMOS transistor (N4).
摘要翻译：具有CMOS电路（CC）的电子设备包括具有第一和第二PMOS晶体管（P1，P2）和第一和第二NMOS晶体管（N1，N2）的第一驱动电路（10）。电子设备还包括具有第三和第四PMOS晶体管（P3，P4）和第三和第四NMOS晶体管（N3，N4）的第二驱动器电路（20）。第二驱动电路（20）与第一驱动电路（10）互补，并与第一驱动电路（10）反向切换。第二和第四PMOS晶体管（P2，P4）的栅极耦合到第一偏置电压（REPp），并且第二和第四NMOS晶体管（N2，N4）的栅极耦合到第二偏置电压（REFn）。第一电容（C3）耦合在第四PMOS晶体管（P4）的栅极和漏极之间，第二电容（C4）耦合在第四NMOS晶体管（N4）的栅极和漏极源之间。

5. 发明申请

WO2004077516A3 OUTPUT CALIBRATOR WITH DYNAMIC PRECISION 审中-公开
标题翻译：具有动态精度的输出校准器
公开(公告)号：WO2004077516A3
公开(公告)日：2005-07-28
申请号：PCT/US2004005462
申请日：2004-02-25
申请人： RAMBUS INC , LEE KUECK HOCK , CHAN ANDY PENG-PUI
发明人： LEE KUECK HOCK , CHAN ANDY PENG-PUI
IPC分类号： H03K17/16 , H03K19/003 , G01R19/00
CPC分类号： H03K17/167 , H03K19/00384
摘要： An integrated circuit device (230) having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver and adjusts the control value by a first increment until a transition event is detected. After the transition event is detected, the control circuit adjusts the control value by a second increment, the second increment being smaller than the first increment.
摘要翻译：一种具有输出驱动电路和控制电路的集成电路装置（230）。输出驱动器电路根据控制值输出具有信号电平的第一信号。控制电路被耦合以从输出驱动器接收第一信号，并且通过第一增量调整控制值，直到检测到转换事件。在检测到转换事件之后，控制电路将控制值调整第二增量，第二增量小于第一增量。

6. 发明申请

WO2005041202A1 RANDOM ACCESS MEMORY HAVING SELF-ADJUSTING OFF-CHIP DRIVER 审中-公开
标题翻译：具有自调节片外驱动器的随机存取存储器
公开(公告)号：WO2005041202A1
公开(公告)日：2005-05-06
申请号：PCT/EP2004/010947
申请日：2004-09-30
申请人： INFINEON TECHNOLOGIES AG , HAN, Jonghee , KIM, Jung, Pill
发明人： HAN, Jonghee , KIM, Jung, Pill
IPC分类号： G11C11/4096
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1069 , G11C11/4096 , H03K19/00384
摘要： One embodiment of the present invention provides a random access memory device (30) including a memory array (32), a level detector (38), and an off-chip driver circuit (40). The level detector (38) monitors a source voltage and provides a level signal representative of a voltage range of the source voltage. The off-chip driver circuit (40) is associated with the memory array (32) and provides an output signal having at least one operating parameter, and adjusts the at least one operating parameter by adjusting a magnitude of at least one impedance based on the level signal.
摘要翻译：本发明的一个实施例提供了一种包括存储器阵列（32），电平检测器（38）和片外驱动电路（40）的随机存取存储器件（30）。电平检测器（38）监视源电压并提供表示源极电压的电压范围的电平信号。芯片外驱动电路（40）与存储器阵列（32）相关联并提供具有至少一个操作参数的输出信号，并且通过基于所述至少一个阻抗的调整来调整所述至少一个操作参数电平信号。

7. 发明申请

WO2004077516A2 OUTPUT CALIBRATOR WITH DYNAMIC PRECISION 审中-公开
标题翻译：具有动态精度的输出校准器
公开(公告)号：WO2004077516A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/005462
申请日：2004-02-25
申请人： RAMBUS INCORPORATED , LEE, Kueck, Hock , CHAN, Andy, Peng-Pui
发明人： LEE, Kueck, Hock , CHAN, Andy, Peng-Pui
IPC分类号： H01L
CPC分类号： H03K17/167 , H03K19/00384
摘要： An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver and adjusts the control value by a first increment until a transition event is detected. After the transition event is detected, the control circuit adjusts the control value by a second increment, the second increment being smaller than the first increment.
摘要翻译：一种具有输出驱动电路和控制电路的集成电路装置。输出驱动器电路根据控制值输出具有信号电平的第一信号。控制电路被耦合以从输出驱动器接收第一信号，并且通过第一增量调整控制值，直到检测到转换事件。在检测到转换事件之后，控制电路将控制值调整第二增量，第二增量小于第一增量。

8. 发明申请

WO99043086A1 DYNAMIC BIAS CIRCUITRY UTILIZING EARLY VOLTAGE CLAMP AND TRANSLINEAR TECHNIQUES 审中-公开
标题翻译：动态偏置电路利用早期电压钳和斜线技术
公开(公告)号：WO99043086A1
公开(公告)日：1999-08-26
申请号：PCT/US1999/002044
申请日：1999-01-28
IPC分类号： G06F1/26 , H03K19/003 , H03K3/01 , H03L5/00
CPC分类号： G06F1/263 , H03K19/00315 , H03K19/00384
摘要： A system utilizes a dynamic feedback bias circuit (115) and includes a first bus agent and a second bus agent. The second bus agent has a core (120) which operates at a core operating voltage. An input device is biased by the dynamic feedback bias circuit.
摘要翻译：系统利用动态反馈偏置电路（115）并且包括第一总线代理和第二总线代理。第二总线代理具有以核心工作电压工作的核心（120）。输入装置被动态反馈偏置电路偏置。

9. 发明申请

WO1994029962A1 CMOS BTL COMPATIBLE BUS AND TRANSMISSION LINE DRIVER 审中-公开
标题翻译： CMOS BTL兼容总线和传输线路驱动器
公开(公告)号：WO1994029962A1
公开(公告)日：1994-12-22
申请号：PCT/US1994005673
申请日：1994-05-20
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , KUO, James, R.
IPC分类号： H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： A driver for providing binary signals from a data system to a transmission line (31) is disclosed. The driver includes a first field-effect transistor (FET) (M1) coupled between an output node (Vout) and ground for conducting current from the output node to ground. The output node is connectable to the transmission line (31). A first input stage (M2, M5, 38) conducts current from a first voltage supply (VDD) to the gate of the first FET. The first input stage includes a voltage sensing (38) amplifier for comparing a reference voltage (VR) to the voltage potential of the output node (Vout) and for controlling the amount of current (ISDM5) conducted to the gate of the first FET (M1) in response to the comparison. A second input stage (M3, M4) conducts current from the gate of the first FET (M1) to ground. In an alternative embodiment, the driver includes a temperature compensation circuit (40) coupled to the first and second input stages for adjusting the level of current conducted to the gate of the first FET (M1) and the level of current conducted from the gate of the first FET to compensate for variations in temperature.
摘要翻译：公开了一种用于从数据系统向传输线（31）提供二进制信号的驱动器。驱动器包括耦合在输出节点（Vout）和接地之间的第一场效应晶体管（M1），用于将电流从输出节点传导到地。输出节点可连接到传输线（31）。第一输入级（M2，M5,38）将电流从第一电压源（VDD）传导到第一FET的栅极。第一输入级包括用于将参考电压（VR）与输出节点（Vout）的电压电位进行比较并用于控制传导到第一FET的栅极的电流量（ISDM5）的电压感测（38）放大器 M1）响应比较。第二输入级（M3，M4）将电流从第一FET（M1）的栅极传导到地。在替代实施例中，驱动器包括耦合到第一和第二输入级的温度补偿电路（40），用于调节传导到第一FET（M1）的栅极的电流电平和从栅极导通的电流电平第一个FET来补偿温度变化。

10. 发明申请

WO1994029799A1 CMOS BUS AND TRANSMISSION LINE RECEIVER 审中-公开
标题翻译： CMOS总线和传输线接收器
公开(公告)号：WO1994029799A1
公开(公告)日：1994-12-22
申请号：PCT/US1994005984
申请日：1994-05-27
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , KUO, James, R.
IPC分类号： G06F13/40
CPC分类号： H04L25/0292 , G05F3/245 , G06F13/4072 , H03K19/00384
摘要： A receiver for providing binary signals from a transmission line to a data system is disclosed. The receiver includes a differencial comparator (22) for comparing a reference voltage to an input voltage and for providing a comparator output signal in response to the comparison. The comparator output signal indicates whether the input voltage is greater or less than the reference voltage. A first current source is coupled to the differential comparator for providing current to the differential comparator. The first current source provides substantially the same amount of current to the differential comparator whether the input voltage is greater or less than the reference voltage, and the first current source has a positive temperature coefficient so that when temperature increases the current provided by the first current source increases. A middle stage (26) amplifies the comparator output signal to produce a middle stage output signal and compensates the middle stage output signal for variations in temperature.
摘要翻译：公开了一种从传输线向数据系统提供二进制信号的接收机。接收器包括用于将参考电压与输入电压进行比较的差分比较器（22），并且用于响应于比较而提供比较器输出信号。比较器输出信号指示输入电压是否大于或小于参考电压。第一电流源耦合到差分比较器，用于向差分比较器提供电流。第一电流源提供与差分比较器基本相同的电流量，无论输入电压是大于还是小于参考电压，并且第一电流源具有正温度系数，使得当温度增加由第一电流提供的电流来源增加。中间级（26）放大比较器输出信号以产生中间级输出信号，并补偿中间级输出信号的温度变化。

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