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1. 发明申请

WO2018093997A2 HIGH ACCURACY VOLTAGE REFERENCES 审中-公开
公开(公告)号：WO2018093997A2
公开(公告)日：2018-05-24
申请号：PCT/US2017/061942
申请日：2017-11-16
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： MCCARTHY, Shaun M. , MUKADAM, Mustansir Y. , WURSTER, Stefan M. , THOMPSON, Barry , SNOW, Dane R.
IPC分类号： G05F3/30
CPC分类号： G05F3/205 , G01K7/01 , G05F3/30
摘要： Two transistors are connected between a power source and separate current references. The base of the first transistor is connected to a bias voltage, and the base of the second transistor is connected to the output of a differential amplifier. The amplifier inputs are connected to the nodes where the transistors are connected to the current references. The transistors and the current references may be of different sizes, such that the output voltage of the amplifier is a function of temperature and of the product of the ratios of the transistors and the current references. A number of switches may be employed such that, in alternative modes of operation, the amplifier is used to buffer the bias voltage, the offset of the amplifier, the output of the first transistor, and/or a stored sample of the temperature output voltage, which are combined to arrive at an adjusted temperature reading.

2. 发明申请

WO2010039444A2 PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANALOG CIRCUITS USING A SINGLE PROCESS 审中-公开
标题翻译：工艺/设计方法使用单一工艺实现高性能逻辑和模拟电路
公开(公告)号：WO2010039444A2
公开(公告)日：2010-04-08
申请号：PCT/US2009057271
申请日：2009-09-17
申请人： ALTERA CORP , XIANG QI , RATNAKUMAR ALBERT , TUNG JEFFREY XIAOQI , DING WEIQI
发明人： XIANG QI , RATNAKUMAR ALBERT , TUNG JEFFREY XIAOQI , DING WEIQI
IPC分类号： H01L27/088 , H01L21/265
CPC分类号： G05F3/205 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
摘要翻译：提出了一种使用正向偏置和改进的混合信号处理的电路设计来提高模拟电路性能的方法。定义了由多个NMOS和PMOS晶体管组成的电路。 NMOS晶体管的体端耦合到第一电压源并且PMOS晶体管的体端耦合到第二电压源。通过将第一电压源施加到每个选定的NMOS晶体管的本体端子并且将第二电压源施加到每个选定的PMOS晶体管的本体端子来选择性地偏置电路中的晶体管。在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的本体端子提供正向和反向偏置。

3. 发明申请

WO2008147780A1 METHOD AND CIRCUIT FOR AN EFFICIENT AND SCALABLE CONSTANT CURRENT SOURCE FOR AN ELECTRONIC DISPLAY 审中-公开
标题翻译：用于电子显示的有效和可定量恒定电流源的方法和电路
公开(公告)号：WO2008147780A1
公开(公告)日：2008-12-04
申请号：PCT/US2008/064271
申请日：2008-05-20
申请人： MSILICA , THANDI, Gurjit, S. , S, Dilip , SANTO, Hendrik , VI, Kien
发明人： THANDI, Gurjit, S. , S, Dilip , SANTO, Hendrik , VI, Kien
IPC分类号： G05F3/16
CPC分类号： G05F3/205
摘要： The present invention uses two transistors instead of a sensing resistor to provide a constant current source for a load such as an array of light emitting diodes ( LEDs ). In the present invention, a bias current is applied to a branch of the circuit. The drain-to-source voltages of two transistors are matched. The voltage at the gate of both transistors is controlled based on the bias current and the drain-to-source current of the first of the two transistors. The second of the two transistors is sized such that source current of the second transistor is a multiple of the source current of the first transistor for a given gate voltage. By the techniques of this invention, the load current in a circuit is efficiently kept constant at a multiple of the input bias current.
摘要翻译：本发明使用两个晶体管而不是感测电阻来为例如发光二极管（LED）阵列的负载提供恒定电流源。在本发明中，偏置电流被施加到电路的支路。两个晶体管的漏极 - 源极电压匹配。基于两个晶体管中的第一个的偏置电流和漏极 - 源极电流来控制两个晶体管的栅极处的电压。两个晶体管中的第二个的尺寸使得第二晶体管的源电流对于给定的栅极电压是第一晶体管的源极电流的倍数。通过本发明的技术，电路中的负载电流被有效地保持恒定在输入偏置电流的倍数。

4. 发明申请

WO1991006979A1 METHOD AND DEVICE FOR COMPENSATING DRIFT IN A SEMICONDUCTOR ELEMENT 审中-公开
标题翻译：用于在半导体元件中补偿干涉的方法和装置
公开(公告)号：WO1991006979A1
公开(公告)日：1991-05-16
申请号：PCT/EP1990001811
申请日：1990-10-26
申请人： INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW , COLINGE, Jean, Pierre
发明人： INTERUNIVERSITAIR MICRO-ELEKTRONICA CENTRUM VZW
IPC分类号： H01L27/02
CPC分类号： G05F3/205 , H01L27/0218
摘要： A method and device for compensating drift wherein a feedback voltage is applied to a region of semiconductor material adjoining the insulating region.
摘要翻译：一种用于补偿漂移的方法和装置，其中反馈电压被施加到邻近绝缘区域的半导体材料的区域。

5. 发明申请

WO2008073745A3 TUNABLE VOLTAGE CONTROLLER FOR A SUB-CIRCUIT AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：用于子电路的可控电压控制器及其操作方法
公开(公告)号：WO2008073745A3
公开(公告)日：2009-01-08
申请号：PCT/US2007086265
申请日：2007-12-03
申请人： TEXAS INSTRUMENTS INC , HOUSTON THEODORE W , CLINTON MICHAEL P , PITTS ROBERT L
发明人： HOUSTON THEODORE W , CLINTON MICHAEL P , PITTS ROBERT L
IPC分类号： H03K3/01 , G11C5/14
CPC分类号： G05F3/205
摘要： The invention (100) provides a tunable voltage controller for use with a sub-circuit (105). In one embodiment, the tunable voltage controller (115) includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit (120) configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.
摘要翻译：本发明（100）提供了一种与子电路（105）一起使用的可调电压控制器。在一个实施例中，可调谐电压控制器（115）包括二极管连接的MOS晶体管，其包含在衬底的掺杂阱中并且被配置为为子电路提供电压。此外，可调谐电压控制器还包括偏置单元（120），其被配置为通过将掺杂阱选择性地连接到多个电压源中的一个或可变电压源来调节电压。

6. 发明申请

WO2007055248A1 電流源回路审中-公开
标题翻译：电流源电路
公开(公告)号：WO2007055248A1
公开(公告)日：2007-05-18
申请号：PCT/JP2006/322292
申请日：2006-11-08
申请人：松下電器産業株式会社 , 能田毅 , 生駒平治
发明人：能田毅 , 生駒平治
IPC分类号： G05F3/24 , H03F3/345 , H03K19/00
CPC分类号： H03F1/30 , G05F3/205 , H03F3/72 , H03F2203/7206
摘要：　従来の電流源回路の構成では、電流源回路の電流出力停止状態から通常動作状態への復帰時間が長い。　第１のＰチャンネルＭＯＳトランジスタ（ＴＲ１）のゲート端子に所定値の電圧を出力するバイアス回路（１０１）の出力と、電圧安定化容量（１０３）の一端とを接続し、第２のＰチャンネルＭＯＳトランジスタ（ＴＲ２）のゲート端子に動作モードに応じて出力電圧の制御が可能な電圧制御回路（１０２）を接続する。この構成により、第２のＰチャンネルＭＯＳトランジスタ（ＴＲ２）を非導通状態にでき、電流源回路（１００）の電流出力が停止可能となる。そしてバイアス回路（１０１）を、電流源回路（１００）の電流出力停止状態である待機モード及び通常動作状態である通常動作モードのいずれにおいても、同じバイアス電圧を出力するものとすることにより、電圧安定化容量（１０３）の電荷は放電されず、待機モードから通常動作モードへの復帰時間を短縮できる。
摘要翻译：常规的电流源电路配置需要用于将电流源电路从当前输出停止状态复位到正常操作状态的长的复位时间。第一P沟道MOS晶体管（TR1）的栅极端子连接到输出预定值电压和稳定电压（103）的一端的偏置电路（101）的输出端，而第二P沟道MOS晶体管的栅极端子 MOS晶体管（TR2）连接到能够根据操作模式控制输出电压的电压控制电路（102）。利用这种结构，第二P沟道MOS晶体管（TR2）可以被设置为非电连接状态，以停止电流源电路（100）的电流输出。偏置电路（101）被设定为当电流源电路（100）的电流输出处于停止状态时，在电流源电路（100）为正常工作，使得电压稳定容量（103）的电荷不被放电，并且可以减少从等待模式到正常工作模式的复位时间。

7. 发明申请

WO03060996A3 ADAPTIVE THRESHOLD VOLTAGE CONTROL WITH POSITIVE BODY BIAS FOR N AND P-CHANNEL TRANSISTORS 审中-公开
标题翻译： N和P沟道晶体管的自适应阈值电压控制，带有正极体偏置
公开(公告)号：WO03060996A3
公开(公告)日：2003-10-16
申请号：PCT/US0301212
申请日：2003-01-15
申请人： HONEYWELL INT INC
发明人： FULKERSON DAVID E
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K17/30 , H03K19/094 , H01L23/00
CPC分类号： G05F3/205
摘要： A threshold control circuit for CMOS transistors wherein the voltage on the body of an n-channel reference transistor is controlled with a feedback circuit to produce a positive voltage on the body and decrease the threshold of the reference transistor to a desired value and the voltage on the body of a p-channel reference transistor is controlled with a feedback circuit to produce a negative voltage on the body and decrease the threshold of the reference transistor to a desired value.
摘要翻译：一种用于CMOS晶体管的阈值控制电路，其中n沟道参考晶体管的主体上的电压由反馈电路控制以在主体上产生正电压并且将参考晶体管的阈值降低到期望值，并且电压开启用反馈电路控制p沟道参考晶体管的主体以在主体上产生负电压并将参考晶体管的阈值减小到期望值。

8. 发明申请

WO1997050167A1 CHARGE PUMP CIRCUIT ARCHITECTURE 审中-公开
标题翻译：充电泵电路架构
公开(公告)号：WO1997050167A1
公开(公告)日：1997-12-31
申请号：PCT/US1997001332
申请日：1997-01-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , LE, Binh, Quang , CHEN, Pau-Ling , HOLLMER, Shane
IPC分类号： H02M03/07
CPC分类号： H02M3/073 , G05F3/205 , H01L27/0222
摘要： A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having an non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time reducing the overall physical size of the charge pump.
摘要翻译：公开了具有快速上升时间和减小的物理面积的电荷泵电路。电荷泵包括具有不均匀系列自举电容器的多个级。通过在各个阶段使用不均匀的电容器，增加充电上升时间，同时降低电荷泵的整体物理尺寸。

9. 发明申请

WO1996021275A1 SUBSTRATE CLAMP FOR NON-ISOLATED INTEGRATED CIRCUITS 审中-公开
标题翻译：非隔离集成电路基板钳
公开(公告)号：WO1996021275A1
公开(公告)日：1996-07-11
申请号：PCT/US1995016625
申请日：1995-12-19
申请人： MAXIM INTEGRATED PRODUCTS, INC.
发明人： MAXIM INTEGRATED PRODUCTS, INC. , BINGHAM, David
IPC分类号： H03K17/16
CPC分类号： G05F3/205 , H03K19/00315
摘要： A substrate clamp (10) for non-isolated integrated circuits that controls the voltage on a substrate (V) so that the substrate is connected to a specific node (VDD) if the parasitic PN diodes at all the circuit nodes (TOUT1-TOUTN) are not forward biased. If a specific node (TOUT1-TOUTN) is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node (V) and maintains itself at a forward biased diode voltage drop away from the powered node (TOUT1-TOUTN). When the node (TOUT1-TOUTN) returns to no longer being forward biased, the substrate (V) is reconnected to the original power supply node (VDD).
摘要翻译：如果所有电路节点（TOUT1-TOUTN）上的寄生PN二极管，则用于非隔离集成电路的衬底钳位器（10）用于控制衬底（V）上的电压，使得衬底连接到特定节点（VDD）没有向前偏见。如果特定节点（TOUT1-TOUTN）随着施加的电压被强制以正向偏置，则衬底与其原始节点（V）断开，并保持自身处于远离有源节点（TOUT1-TOUTN）的正向偏置二极管电压降）。当节点（TOUT1-TOUTN）返回到不再正向偏置时，衬底（V）重新连接到原始电源节点（VDD）。

10. 发明申请

WO1994001890A1 INTEGRATED CMOS SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：集成CMOS半导体电路
公开(公告)号：WO1994001890A1
公开(公告)日：1994-01-20
申请号：PCT/DE1993000443
申请日：1993-05-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KÖTZLE, Gunther , KREUTER, Volker , LUDWIG, Thomas , SCHETTLER, Helmut
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION
IPC分类号： H01L27/02
CPC分类号： H01L27/0222 , G05F3/205
摘要： An integrated CMOS semiconductor circuit to reduce power consumption in which at least one transistor pair can be operated stably at different supply voltage in that each supply voltage is allocated a threshold voltages which is adjustable via the trough and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the trough to a trough bias voltage generator circuit which, dependently upon an input signal representing the height of the supply voltage, sets the height of the bias voltage corresponding to the supply voltage in order to match the threshold voltage to the supply voltage concerned in such a way that the stable operation of the transistor pair is ensured at all times. A data processing system associated to the integrated semiconductor circuit, which, for example, operates at a supply voltage of 3.6 V, a clock frequency of 66 MHz and a relative power consumption of 1, after switching over to a supply voltage of 1.2 V and a clock frequency of below 5 MHz/attains a power consumption of less than 0.01 and an approximately hundredfold increase in the running time for a battery-operated PC.

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