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1. 发明申请

WO2012006049A1 THREE DIMENSIONAL WIRE BOND INDUCTOR AND TRANSFORMER 审中-公开
标题翻译：三维线束电感和变压器
公开(公告)号：WO2012006049A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/042094
申请日：2011-06-28
申请人： QUALCOMM INCORPORATED , PARK, Sang-June , KIM, Jonghae , NOWAK, Matthew, M. , CICCARELLI, Steve, C
发明人： PARK, Sang-June , KIM, Jonghae , NOWAK, Matthew, M. , CICCARELLI, Steve, C
IPC分类号： H01F17/00 , H01F27/28 , H01L23/64
CPC分类号： H01F27/2804 , H01F17/0006 , H01F2027/2814 , H01L23/5225 , H01L23/5227 , H01L23/645 , H01L2224/48091 , H01L2224/4813 , H01L2224/73265 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional inductor or transformer for an electronic packaging system that includes a plurality of conductive traces and a plurality of conductive wire bonds. The traces are located in a single layer, and each have a first and second pad. Each of the wire bonds couples the second pad of one trace to the first pad of another trace. The trace and wire bonds create a continuous conductive path from the first pad of a first trace to the second pad of a last trace. Passing a current from the first trace to the last trace creates an electromagnetic field between the single layer and the wire bonds. The transformer includes two independent and electromagnetically coupled inductors that can be interleaved. The continuous conductive path can be solenoid-shaped. A shielding layer can also be included that blocks the substrate from the electromagnetic field of the inductor or transformer.
摘要翻译：一种用于电子封装系统的三维电感器或变压器，其包括多个导电迹线和多个导电引线键合。迹线位于单个层中，并且每个具有第一和第二焊盘。每个线接合将一个迹线的第二个焊盘耦合到另一个迹线的第一个焊盘。迹线和引线键形成从第一迹线的第一焊盘到最后迹线的第二焊盘的连续传导路径。将电流从第一个轨迹传递到最后一个轨迹会在单层和引线键之间产生电磁场。该变压器包括可以交错的两个独立的和电磁耦合的电感器。连续导电路径可以是螺线管形的。还可以包括阻挡基板与电感器或变压器的电磁场的屏蔽层。

2. 发明申请

WO2011044390A1 APPARATUS AND METHOD FOR THROUGH SILICON VIA IMPEDANCE MATCHING 审中-公开
标题翻译：通过阻抗匹配通过硅的装置和方法
公开(公告)号：WO2011044390A1
公开(公告)日：2011-04-14
申请号：PCT/US2010/051866
申请日：2010-10-07
申请人： QUALCOMM INCORPORATED , KIM, Jonghae , YANG, Jeong, Hwan , NOWAK, Matthew, M.
发明人： KIM, Jonghae , YANG, Jeong, Hwan , NOWAK, Matthew, M.
IPC分类号： H01L23/64 , H01L23/66 , H01L25/065 , H01L23/522
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/3011
摘要： Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.
摘要翻译：提出了用于匹配倒装芯片电路组件中的阻抗的方法和装置。用于匹配倒装芯片电路组件中的阻抗的装置可以包括与第一管芯相连的第一电路和将第一电路耦合到第二电路的通硅通孔（TSV）。该装置还可以包括插在TSV和第二电路之间的第一阻抗匹配电感器。用于匹配倒装芯片电路组件中的阻抗的方法可以包括提供具有第一电路的管芯，并在管芯上形成TSV。该方法还可以包括提供第二电路并形成插在TSV和第二电路之间的第一阻抗匹配电感器。

3. 发明申请

WO2009129283A1 MANUFACTURING METHOD OF A MAGNETIC TUNNEL JUNCTION ELEMENT USING TWO MASKS 审中-公开
标题翻译：使用两个掩模的磁性隧道结构元件的制造方法
公开(公告)号：WO2009129283A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040612
申请日：2009-04-15
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer (36) containing an exposed first interconnect metallization, (37) a first electrode, (30) a fixed magnetization layer, (32) a tunneling barrier layer, (12) a free magnetization layer (11) and a second electrode (6). An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer (40) encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode (15) is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer (8) covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：用于使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层（36）上沉积（37）第一电极，（30）固定磁化层，（32）隧道势垒层，（12）自由磁化层（11）和第二电极（6）。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层（40）封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极（15）。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二介电钝化层（8）覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

4. 发明申请

WO2012027423A2 WIDE INPUT OUTPUT MEMORY WITH LOW DENSITY, LOW LATENCY AND HIGH DENSITY, HIGH LATENCY BLOCKS 审中-公开
标题翻译：宽输入输出存储器，低密度，低密度和高密度，高延迟块
公开(公告)号：WO2012027423A2
公开(公告)日：2012-03-01
申请号：PCT/US2011/048885
申请日：2011-08-24
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
发明人： GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
IPC分类号： H01L23/48 , G11C11/4076
CPC分类号： G11C11/4076 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
摘要翻译：具有高密度，高延迟的存储器块的外部存储器; 和低密度，低延迟的存储器块。两个存储器块可以被一个或多个处理功能单元单独访问。访问可以是直接存储器访问，或者通过总线或结构交换机。通孔通孔可以将外部存储器连接到包括一个或多个处理功能单元的管芯。

5. 发明申请

WO2009137286A1 3-D INTEGRATED CIRCUIT LATERAL HEAT DISSIPATION 审中-公开
标题翻译： 3-D集成电路横向散热
公开(公告)号：WO2009137286A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/041780
申请日：2009-04-27
申请人： QUALCOMM INCORPORATED , KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew, M.
发明人： KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L25/065 , H01L23/367 , H01L23/373
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/01019
摘要： By filling an air gap between tiers (31,32) of a stacked IC device with a thermally conductive material (320) heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal materia can be electrically insulating. Through silicon-vias (331) can be constructe at certain locations to assist in heat dissipation away from thermally troubled locations (310).
摘要翻译：通过在层叠的IC器件的层（31,32）之间填充导热材料（320），在层之一内的一个或多个位置处产生的热可以横向移位。热的横向位移可以沿着层的整个长度，并且热材料可以是电绝缘的。通过硅通孔（331）可以在某些位置处构造以帮助远离热故障位置（310）的散热。

6. 发明申请

WO2014197364A1 SYSTEMS FOR REDUCING MAGNETIC COUPLING IN INTEGRATED CIRCUITS (ICs), AND RELATED COMPONENTS AND METHODS 审中-公开
标题翻译：用于减少集成电路（IC）中的磁耦合的系统及相关组件和方法
公开(公告)号：WO2014197364A1
公开(公告)日：2014-12-11
申请号：PCT/US2014/040490
申请日：2014-06-02
申请人： QUALCOMM INCORPORATED
发明人： ZUO, Chengjie , KIM, Jonghae , KIM, Daeik, D. , VELEZ, Mario, Francisco , YUN, Changhan , LAN, Je-Hsiung , MIKULKA, Robert, P. , NOWAK, Matthew, M.
IPC分类号： H03H7/46
CPC分类号： H03H7/463 , H03H3/00 , Y10T29/4902
摘要： Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.
摘要翻译：公开了用于减小集成电路（IC）中的磁耦合的系统。还公开了相关的部件和方法。 IC具有多个电感器。每个电感器产生具有可辨别轴线的磁通量。为了减小电感器之间的磁耦合，磁通轴被设计成不平行。特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。这种布置可以特别适用于具有低通和高通滤波器的双工器。

7. 发明申请

WO2014182556A1 TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS 审中-公开
标题翻译：三维（3D）集成电路（IC）（3DIC）及相关组件和方法中的可执行程序
公开(公告)号：WO2014182556A1
公开(公告)日：2014-11-13
申请号：PCT/US2014/036524
申请日：2014-05-02
申请人： QUALCOMM INCORPORATED
发明人： ZUO, Chengjie , KIM, Daeik, D. , LAN, Je-Hsiung , KIM, Jonghae , VELEZ, Mario, Francisco , YUN, Changhan , BERDY, David, F. , MIKULKA, Robert, P. , NOWAK, Matthew, M. , ZHANG, Xiangdong , SEE, Puay, H.
IPC分类号： H03H7/46
CPC分类号： H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
摘要： Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
摘要翻译：公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

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