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1. 发明申请

WO2016106197A3 METAL-INSULATOR-METAL (MIM) CAPACITORS ARRANGED IN A PATTERN TO REDUCE INDUCTANCE, AND RELATED METHODS 审中-公开
公开(公告)号：WO2016106197A3
公开(公告)日：2016-06-30
申请号：PCT/US2015/067052
申请日：2015-12-21
申请人： QUALCOMM INCORPORATED
发明人： YUN, Changhan, Hobie , LAN, Je-Hsiung, Jeffrey , KIM, Daeik, Daniel , BERDY, David, Francis , ZUO, Chengjie , KIM, Jonghae , MUDAKATTE, Niranjan, Sunil , VELEZ, Mario, Francisco , MIKULKA, Robert, Paul
IPC分类号： H01L27/08 , H01L49/02
摘要： Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.

2. 发明申请

WO2014182445A1 ELECTRONIC DEVICE HAVING ASYMMETRICAL THROUGH GLASS VIAS 审中-公开
标题翻译：通过玻璃VIAS不对称的电子设备
公开(公告)号：WO2014182445A1
公开(公告)日：2014-11-13
申请号：PCT/US2014/035041
申请日：2014-04-22
申请人： QUALCOMM INCORPORATED
发明人： KIM, Daeik, D. , BERDY, David, F. , ZUO, Chengjie , VELEZ, Mario, Francisco , YUN, Changhan , MIKULKA, Robert, P. , KIM, Jonghae , LAN, Je-hsiung
IPC分类号： H01F27/28
CPC分类号： H05K9/002 , H01F17/0006 , H01F27/362 , H01F2017/002 , H05K1/115 , H05K3/0017 , H05K3/107
摘要： An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross sectional shape than the second via.
摘要翻译：电子设备包括结构。该结构包括第一组直通玻璃通孔（TGV）和第二组TGV。第一组TGV包括第一通孔，第二组TGV包括第二通孔。第一通孔具有与第二通孔不同的截面形状。

3. 发明申请

WO2018026447A1 SIDE-ASSEMBLED PASSIVE DEVICES 审中-公开
标题翻译：侧面组装的被动装置
公开(公告)号：WO2018026447A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/039262
申请日：2017-06-26
申请人： QUALCOMM INCORPORATED
发明人： BERDY, David, Francis , YUN, Changhan, Hobie , ZUO, Chengjie , MUDAKATTE, Niranjan, Sunil , VELEZ, Mario, Francisco , GU, Shiqun , KIM, Jonghae
IPC分类号： H05K1/02 , H05K1/14 , H01L23/64
摘要： An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.
摘要翻译：集成电路器件包括具有接地平面的第一基板。集成电路器件还包括第二衬底。第二衬底具有第一层无源器件。无源器件在第二衬底的第一侧上包括至少一个电感器。第一层无源器件与接地平面和第一衬底支撑的第二衬底基本正交。电感磁场基本上与地平面平行。

4. 发明申请

WO2014182556A1 TUNABLE DIPLEXERS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DIC) AND RELATED COMPONENTS AND METHODS 审中-公开
标题翻译：三维（3D）集成电路（IC）（3DIC）及相关组件和方法中的可执行程序
公开(公告)号：WO2014182556A1
公开(公告)日：2014-11-13
申请号：PCT/US2014/036524
申请日：2014-05-02
申请人： QUALCOMM INCORPORATED
发明人： ZUO, Chengjie , KIM, Daeik, D. , LAN, Je-Hsiung , KIM, Jonghae , VELEZ, Mario, Francisco , YUN, Changhan , BERDY, David, F. , MIKULKA, Robert, P. , NOWAK, Matthew, M. , ZHANG, Xiangdong , SEE, Puay, H.
IPC分类号： H03H7/46
CPC分类号： H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
摘要： Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
摘要翻译：公开了三维（3D）集成电路（IC）（3DIC）中的可调谐双工器。在一个实施例中，可调谐双工器可以通过在双工器中提供变容二极管或可变电感器之一来形成。可变电抗器或可变电感器的可变特性允许调谐双工器中的陷波，以便选择频带停止以消除期望频率处的谐波以及控制通带的截止频率。通过将双工器的元件堆叠成三维空间是保守的，并且可以使用各种变容二极管和电感器。

5. 发明申请

WO2016011313A1 SUPERPOSED STRUCTURE 3D ORTHOGONAL THROUGH SUBSTRATE INDUCTOR 审中-公开
标题翻译：通过基板电感的超立体结构3D正交
公开(公告)号：WO2016011313A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/040845
申请日：2015-07-17
申请人： QUALCOMM INCORPORATED
发明人： BERDY, David, Francis , ZUO, Chengjie , KIM, Daeik, Daniel , YUN, Changhan, Hobie , VELEZ, Mario, Francisco , MIKULKA, Robert, Paul , KIM, Jonghae
IPC分类号： H01L49/02 , H01F41/04 , H01F17/00
CPC分类号： H01F41/041 , H01F17/0013 , H01F27/2804 , H01F27/29 , H01F2017/004 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) orthogonal inductor pair (700) is embedded in and supported by a substrate (701), and has a first inductor (702) having a first coil that winds around a first winding axis and a second inductor (706) having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
摘要翻译：三维（3D）正交电感器对（700）被嵌入并由衬底（701）支撑，并且具有第一电感器（702），其具有卷绕第一绕组轴线的第一线圈和第二电感器（706））具有围绕第二卷绕轴线缠绕的第二线圈。第二卷绕轴线与第一卷绕轴线正交。第二绕组轴线在第一绕组轴线处于衬底内的交点处。

6. 发明申请

WO2015108652A1 NESTED THROUGH GLASS VIA TRANSFORMER 审中-公开
标题翻译：通过变压器通过玻璃镶嵌
公开(公告)号：WO2015108652A1
公开(公告)日：2015-07-23
申请号：PCT/US2014/070851
申请日：2014-12-17
申请人： QUALCOMM INCORPORATED
发明人： KIM, Daeik, Daniel , KIM, Jonghae , ZUO, Chengjie , VELEZ, Mario, Francisco , YUN, Changhan, Hobie
IPC分类号： H01F27/28
CPC分类号： H01F41/041 , H01F27/2804 , H01F41/00 , H01F2017/0086 , H01F2027/2809 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.
摘要翻译： 3D嵌套变压器包括具有与一组迹线菊花链连接的一组通过衬底通孔的衬底。至少一些直通衬底通孔具有第一和第二导电区域。该组迹线还包括将至少一些贯穿衬底通孔的第一导电区域耦合在一起的第一组迹线，以及将至少一些第二导电区域耦合在一起的第二组迹线。

7. 发明申请

WO2010151814A1 HIGH DENSITY MIM CAPACITOR EMBEDDED IN A SUBSTRATE 审中-公开
标题翻译：埋在基板中的高密度MIM电容
公开(公告)号：WO2010151814A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040061
申请日：2010-06-25
申请人： QUALCOMM Incorporated , SWEENEY, Fifin , VELEZ, Mario, Francisco , PAN, Yuancheng, Christopher , GU, Shiqun
发明人： SWEENEY, Fifin , VELEZ, Mario, Francisco , PAN, Yuancheng, Christopher , GU, Shiqun
IPC分类号： H01L23/64 , H01L23/498 , H01L23/50 , H01G4/33 , H01G4/40
CPC分类号： H01L23/642 , H01G4/33 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L25/0657 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/15311 , H01L2924/15312 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.
摘要翻译：集成电路封装包括去耦电容器。集成电路封装还包括封装基板。去耦电容器至少部分地嵌入在封装衬底中。集成电路封装还包括安装到封装衬底的管芯。管芯耦合到去耦电容器。芯片从去耦电容器接收基本上瞬时的电流。

8. 发明申请

WO2017165101A1 PASSIVE DEVICE ASSEMBLY FOR ACCURATE CONTROL OF THE DISTANCE TO A GROUND PLANE 审中-公开
标题翻译：用于精确控制到地平面距离的被动装置组件
公开(公告)号：WO2017165101A1
公开(公告)日：2017-09-28
申请号：PCT/US2017/020601
申请日：2017-03-03
申请人： QUALCOMM INCORPORATED
发明人： ZUO, Chengjie , BERDY, David, Francis , KIM, Daeik, Daniel , YUN, Changhan, Hobie , VELEZ, Mario, Francisco , KIM, Jonghae
IPC分类号： H05K1/14 , H05K1/02 , H01L23/538 , H01L23/552
摘要： Passive device assembly (202) for accurate ground plane control is disclosed. A passive device assembly includes a device substrate (214) conductively coupled to a ground plane separation control substrate (216). A passive device (204) disposed on a lower surface (220) of the device substrate is separated from an embedded ground plane (210) mounted on a lower surface of the ground plane separation control substrate by a separation distance (D1). The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads (212) are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
摘要翻译：公开了用于精确地平面控制的无源装置组件（202）。无源器件组件包括导电耦合到接地平面分离控制衬底（216）的器件衬底（214）。布置在器件基板的下表面（220）上的无源器件（204）与安装在接地平面分离控制基板的下表面上的嵌入式接地平面（210）隔开分离距离（D1）。精确控制分离距离以最小化无源设备可能发生的不希望的干扰。分离距离设置在无源装置组件内部。导电安装垫（212）设置在接地平面分离控制衬底的下表面上，以支持无源装置组件在电路板上的精确对准。通过在无源器件组件内提供足够的分离距离，无源器件组件可以精确地安装到任何电路板上，而不管电路板的具体设计和布局。

9. 发明申请

WO2017023439A1 TUNABLE CAVITY RESONATOR 审中-公开
标题翻译：可调节腔谐振器
公开(公告)号：WO2017023439A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/039053
申请日：2016-06-23
申请人： QUALCOMM INCORPORATED
发明人： BERDY, David, Francis , ZUO, Chengjie , LAN, Je-Hsiung, Jeffrey , KIM, Daeik, Daniel , YUN, Changhan, Hobie , VELEZ, Mario, Francisco , KIM, Jonghae
IPC分类号： H01P7/06
CPC分类号： H01P7/06 , H01P7/10
摘要： An apparatus includes a tunable cavity resonator that includes conductive walls that form a tunable cavity. The tunable cavity has first dimensions when one or more phase change material layers within the tunable cavity have a first state. The tunable cavity has second dimensions when the one or more phase change material layers have a second state.
摘要翻译：一种装置包括可调谐腔谐振器，其包括形成可调谐空腔的导电壁。当可调谐腔内的一个或多个相变材料层具有第一状态时，可调谐腔具有第一尺寸。当一个或多个相变材料层具有第二状态时，可调谐腔具有第二维度。

10. 发明申请

WO2014197364A1 SYSTEMS FOR REDUCING MAGNETIC COUPLING IN INTEGRATED CIRCUITS (ICs), AND RELATED COMPONENTS AND METHODS 审中-公开
标题翻译：用于减少集成电路（IC）中的磁耦合的系统及相关组件和方法
公开(公告)号：WO2014197364A1
公开(公告)日：2014-12-11
申请号：PCT/US2014/040490
申请日：2014-06-02
申请人： QUALCOMM INCORPORATED
发明人： ZUO, Chengjie , KIM, Jonghae , KIM, Daeik, D. , VELEZ, Mario, Francisco , YUN, Changhan , LAN, Je-Hsiung , MIKULKA, Robert, P. , NOWAK, Matthew, M.
IPC分类号： H03H7/46
CPC分类号： H03H7/463 , H03H3/00 , Y10T29/4902
摘要： Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.
摘要翻译：公开了用于减小集成电路（IC）中的磁耦合的系统。还公开了相关的部件和方法。 IC具有多个电感器。每个电感器产生具有可辨别轴线的磁通量。为了减小电感器之间的磁耦合，磁通轴被设计成不平行。特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。这种布置可以特别适用于具有低通和高通滤波器的双工器。

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