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1. 发明申请

WO2012094481A2 MEMORY ADDRESS TRANSLATION 审中-公开
标题翻译：存储器地址转换
公开(公告)号：WO2012094481A2
公开(公告)日：2012-07-12
申请号：PCT/US2012/020312
申请日：2012-01-05
申请人： MICRON TECHNOLOGY, INC. , MANNING, Troy, A. , CULLEY, Martin, L. , LARSEN, Troy, D.
发明人： MANNING, Troy, A. , CULLEY, Martin, L. , LARSEN, Troy, D.
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
摘要： The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译：本公开包括用于存储器地址转换的设备，系统和方法。一个或多个实施例包括存储器阵列和耦合到阵列的控制器。该阵列包括具有多个记录的第一表格，其中每个记录包括多个条目，其中每个条目包括与存储在阵列中的数据段相对应的物理地址和逻辑地址。控制器包括具有多个记录的第二表格，其中每个记录包括多个条目，其中每个条目包括对应于第一表格中的记录的物理地址和逻辑地址。控制器还包括具有多个记录的第三表格，其中每个记录包括多个条目，其中每个条目包括对应于第二表格中的记录的物理地址和逻辑地址。

2. 发明申请

WO2005073974A1 MEMORY DEVICE HAVING MULTIPLE-FUNCTION STROBE TERMINALS 审中-公开
标题翻译：具有多功能结构端子的存储器件
公开(公告)号：WO2005073974A1
公开(公告)日：2005-08-11
申请号：PCT/US2005/000809
申请日：2005-01-11
申请人： MICRON TECHNOLOGY, INC. , CHOI, Joo, S. , MANNING, Troy, A.
发明人： CHOI, Joo, S. , MANNING, Troy, A.
IPC分类号： G11C7/22
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/1066 , G11C7/1072 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.
摘要翻译：存储器件具有数据收发器，写选通收发器和读选通收发器。数据收发器将输入数据传输到存储器件并从存储器件传送输出数据。写入选通收发器传送输入数据的定时信息。读选通收发器传输输出数据的定时信息。存储装置还具有用于产生辅助信息的辅助电路。辅助信息包括与输入数据和输出数据的定时信息不同的信息。辅助电路使用写入和读取收发器将辅助信息传送到存储器件和从存储器件传送辅助信息。

3. 发明申请

WO2007005218A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：WO2007005218A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY, INC. , MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
发明人： MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

4. 发明申请

WO2004001846A2 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A2
公开(公告)日：2003-12-31
申请号：PCT/US2003/021029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY, INC. , BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
发明人： BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

5. 发明申请

WO2010016879A1 ROW MASK ADDRESSING 审中-公开
标题翻译： ROW MASK寻址
公开(公告)号：WO2010016879A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/004443
申请日：2009-08-03
申请人： MICRON TECHNOLOGY, INC. , MANNING, Troy, A.
发明人： MANNING, Troy, A.
IPC分类号： G11C8/00 , G11C8/10 , G11C8/18 , G11C8/08
CPC分类号： G11C8/10 , G11C11/4087
摘要： Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.
摘要翻译：电子设备，系统和方法可以操作结构以访问存储器阵列的行的一部分而不访问整个行。公开了附加装置，系统和方法。

6. 发明申请

WO2006121874A2 MEMORY DEVICE AND METHOD HAVING A DATA BYPASS PATH TO ALLOW RAPID TESTING AND CALIBRATION 审中-公开
标题翻译：具有数据旁路的存储器件和方法允许快速测试和校准
公开(公告)号：WO2006121874A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/017439
申请日：2006-05-04
申请人： MICRON TECHNOLOGY, INC. , JOHNSON, James, B. , MANNING, Troy, A.
发明人： JOHNSON, James, B. , MANNING, Troy, A.
IPC分类号： G06F13/00
CPC分类号： G11C7/1039 , G11C7/1048 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/105 , G11C2207/2254
摘要： A synchronous dynamic random access memory ("SDRAM") device includes a pipelined write data path coupling data from a data bus to a DRAM array, and a pipelined read data path coupling read data from the array to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without first being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.
摘要翻译：同步动态随机存取存储器（“SDRAM”）器件包括将从数据总线到DRAM阵列的数据耦合的流水线写入数据路径，以及将读取数据从阵列耦合到数据总线的流水线读取数据路径。 SDRAM器件还包括允许写入数据路径中的写入数据直接耦合到读取数据路径而不首先存储在DRAM阵列中的旁路路径。写数据优选地通过向DRAM设备发出写命令而通过写数据路径耦合，并且读数据优选地通过向DRAM设备发出读命令而通过读数据路径耦合。禁止存储器阵列响应这些命令，使得写数据不存储在阵列中，并且从阵列读取数据不耦合到读数据路径。

7. 发明申请

WO2002099661A3 METHOD AND APPARATUS FOR DETERMINING ACTUAL WRITE LATENCY AND ACCURATELY ALIGNING THE START OF DATA CAPTURE WITH THE ARRIVAL OF DATA AT A MEMORY DEVICE 审中-公开
公开(公告)号：WO2002099661A3
公开(公告)日：2002-12-12
申请号：PCT/US2002/017849
申请日：2002-06-06
申请人： MICRON TECHNOLOGY, INC.
发明人： JOHNSON, Brian , KEETH, Brent , MANNING, Troy, A.
IPC分类号： G11C7/10
摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with the predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.

8. 发明申请

WO1996020479A1 BURST EDO MEMORY DEVICE ADDRESS COUNTER 审中-公开
标题翻译： BURST EDO存储设备地址计数器
公开(公告)号：WO1996020479A1
公开(公告)日：1996-07-04
申请号：PCT/US1995016656
申请日：1995-12-21
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , ONG, Adrian, E. , ZAGAR, Paul, S. , WILLIAMS, Brett, L. , MANNING, Troy, A.
IPC分类号： G11C07/00
CPC分类号： G11C7/109 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407
摘要： An integrated memory circuit is described which has a counter for producing a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). The address is changed in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer. The memory includes a generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access.
摘要翻译：描述了具有用于产生顺序或交错地址序列的计数器的集成存储器电路。所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。响应于列地址信号（CAS *）的上升沿改变地址。存储器还包括缓冲电路，其响应于列地址信号的下降沿而锁存地址计数器的输出。使用缓冲器中锁存的地址，在列地址信号的下降沿以突发方式访问存储单元。存储器包括用于基于外部列地址信号产生内部控制信号的发生器电路。发生器电路检测列地址信号的第一有效转换和列地址信号的第一无效转换。将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化设备以进行另一个突发存取。

9. 发明申请

WO2002073619A2 SYSTEM LATENCY LEVELIZATION FOR READ DATA 审中-公开
标题翻译：用于读取数据的系统延迟级别
公开(公告)号：WO2002073619A2
公开(公告)日：2002-09-19
申请号：PCT/US2002/007226
申请日：2002-03-12
申请人： MICRON TECHNOLOGY, INC.
发明人： JANZEN, Jeffery, W. , BRENT, Keeth , RYAN, Kevin, J. , MANNING, Troy, A. , JOHNSON, Brian
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
摘要翻译：在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统读延迟。

10. 发明申请

WO2002069341A2 A METHOD OF SYNCHRONIZING READ TIMING IN A HIGH SPEED MEMORY SYSTEM 审中-公开
标题翻译：在高速存储器系统中同步读取时序的方法
公开(公告)号：WO2002069341A2
公开(公告)日：2002-09-06
申请号：PCT/US2002/002764
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： JANZEN, Jeffery, W. , MANNING, Troy, A. , MARTIN, Chris, G. , KEETH, Brent
IPC分类号： G11C7/22
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
摘要翻译：通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。然后将延迟应用于在存储器系统的常规操作期间读取事务。

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