专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007005218A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：WO2007005218A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY, INC. , MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
发明人： MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

2. 发明申请

WO2004001846A2 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A2
公开(公告)日：2003-12-31
申请号：PCT/US2003/021029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY, INC. , BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
发明人： BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

3. 发明申请

WO1998014953A1 ANTIFUSE DETECTION CIRCUIT 审中-公开
标题翻译：抗体检测电路
公开(公告)号：WO1998014953A1
公开(公告)日：1998-04-09
申请号：PCT/US1997017985
申请日：1997-10-03
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , CASPER, Stephen, L. , MARTIN, Chris, G.
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
摘要翻译：描述了使用锁存电路和两个反熔丝的反熔丝检测电路。反熔丝耦合在锁存电路和地之间。所描述的锁存电路是可以检测两个反熔丝中的哪一个已被编程的差分电路。该电路精确检测在编程后具有较高电阻的反熔丝。

4. 发明申请

WO2002069341A2 A METHOD OF SYNCHRONIZING READ TIMING IN A HIGH SPEED MEMORY SYSTEM 审中-公开
标题翻译：在高速存储器系统中同步读取时序的方法
公开(公告)号：WO2002069341A2
公开(公告)日：2002-09-06
申请号：PCT/US2002/002764
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： JANZEN, Jeffery, W. , MANNING, Troy, A. , MARTIN, Chris, G. , KEETH, Brent
IPC分类号： G11C7/22
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
摘要翻译：通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。然后将延迟应用于在存储器系统的常规操作期间读取事务。

5. 发明申请

WO1998015958A1 CHARGE SHARING DETECTION CIRCUIT FOR ANTI-FUSES 审中-公开
标题翻译：充电共享检测电路
公开(公告)号：WO1998015958A1
公开(公告)日：1998-04-16
申请号：PCT/US1997018063
申请日：1997-10-07
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , MARTIN, Chris, G. , CASPER, Stephen, L.
IPC分类号： G11C07/06
CPC分类号： G11C17/18 , G11C7/06
摘要： A detection circuit for detecting unblown and blown conditions for an anti-fuse. The detection circuit includes a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval, and a sampling circuit for coupling the anti-fuse to the detection node to provide a voltage at the detection node that is indicative of the ability of the anti-fuse to retain a charge during the discharge time interval. An output circuit that is coupled to the detection node is responsive to the voltage provided at the detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.
摘要翻译：一种用于检测用于反熔丝的未吹制和吹制条件的检测电路。检测电路包括预充电电路，用于在预充电时间间隔期间向反熔丝施加预充电;以及采样电路，用于将反熔丝耦合到检测节点，以在检测节点处提供指示能力的电压的反熔丝在放电时间间隔期间保持电荷。耦合到检测节点的输出电路响应于在检测节点处提供的电压，以提供用于指示用于反熔丝的未吹扫状态的第一输出和用于指示用于反熔丝的吹出状态的第二输出。

6. 发明申请

WO2002069132A3 IMPROVED HIGH SPEED DATA CAPTURE CIRCUIT FOR A DIGITAL DEVICE 审中-公开
公开(公告)号：WO2002069132A3
公开(公告)日：2002-09-06
申请号：PCT/US2002/002758
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： KEETH, Brent , MARTIN, Chris, G.
IPC分类号： G06F7/00
摘要： A data capture circuit for an integrated circuit is disclosed which includes providing respective data paths between a latch and clock terminal and a latch and an associated data terminal, the length of each of the paths for a given latch device being approximately equal.

7. 发明申请

WO2003047104A1 ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS 审中-公开
标题翻译：主动终止电路和控制外部集成电路端子阻抗的方法
公开(公告)号：WO2003047104A1
公开(公告)日：2003-06-05
申请号：PCT/US2002/037454
申请日：2002-11-20
申请人： MICRON TECHNOLOGY, INC.
发明人： MARTIN, Chris, G.
IPC分类号： H03K17/16
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1078 , G11C11/4093 , G11C2207/105 , G11C2207/2254
摘要： An active termination circuit (90) is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit (110) that generates a first control signal to set the impedance of another PMOS transistor (134) to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor (144) to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.
摘要翻译：有源终端电路（90）用于设定多个输入端的输入阻抗。每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管（134）的阻抗设置为等于第一预定电阻的控制电路（110）来控制，并产生第二控制信号以设置阻抗的另一NMOS晶体管（144）等于第二预定电阻。第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式