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1. 发明申请

WO2021236324A1 OPERATIONAL CODE STORAGE FOR AN ON-DIE MICROPROCESSOR 审中-公开
公开(公告)号：WO2021236324A1
公开(公告)日：2021-11-25
申请号：PCT/US2021/030812
申请日：2021-05-05
申请人： MICRON TECHNOLOGY, INC.
发明人： MANNING, Troy A. , HARMS, Jonathan D. , LARSEN, Troy D. , HUSH, Glen E. , FINKBEINER, Timothy P.
IPC分类号： G06F15/78 , G06F12/06 , G06F13/16 , G06F9/4401 , G06F9/445
摘要： Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

2. 发明申请

WO2020081193A1 MEMORY DEVICE PROCESSING 审中-公开
公开(公告)号：WO2020081193A1
公开(公告)日：2020-04-23
申请号：PCT/US2019/052365
申请日：2019-09-23
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , LARSEN, Troy D.
IPC分类号： G11C11/4091 , G11C8/12 , G11C11/408 , G06F3/06
摘要： Embodiments described herein include apparatuses and methods for memory device processing. More specifically, an example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks. The processing -in-memory device of the example apparatus may save time and/or power by reducing and/or eliminating external communications.

3. 发明申请

WO2019046032A9 PROCESSING IN MEMORY 审中-公开
公开(公告)号：WO2019046032A9
公开(公告)日：2019-03-07
申请号：PCT/US2018/047172
申请日：2018-08-21
申请人： MICRON TECHNOLOGY, INC.
发明人： LEA, Perry V. , FINKBEINER, Timothy P.
IPC分类号： G06F13/16 , G06F3/06 , G11C7/06 , G11C7/22 , G11C11/4091 , G11C11/4076
摘要： Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

4. 发明申请

WO2017120273A1 ERROR CODE CALCULATION ON SENSING CIRCUITRY 审中-公开
标题翻译：感应电路的误码计算
公开(公告)号：WO2017120273A1
公开(公告)日：2017-07-13
申请号：PCT/US2017/012240
申请日：2017-01-05
申请人： MICRON TECHNOLOGY, INC.
发明人： LEA, Perry V. , FINKBEINER, Timothy P.
IPC分类号： G06F11/16 , G06F11/10
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G06F12/00 , G11C7/06 , G11C7/062 , G11C7/1006 , G11C7/1048 , G11C7/1087 , G11C7/12 , G11C11/4091 , G11C11/4096 , G11C29/46 , G11C29/52 , H03M13/09
摘要： Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.
摘要翻译：本公开的示例提供用于错误代码计算的装置和方法。该设备可以包括耦合到感测线的存储器单元的阵列。该设备可以包括控制器，该控制器被配置为控制耦合到感测线的感测电路以执行多个操作而不经由输入/输出（I / O）线传输数据。可以控制感测电路来计算存储在存储单元阵列中的数据的错误代码，并将错误代码与数据的初始错误代码进行比较，以确定数据是否已被修改。

5. 发明申请

WO2018200358A1 ACCESSING DATA IN MEMORY 审中-公开
公开(公告)号：WO2018200358A1
公开(公告)日：2018-11-01
申请号：PCT/US2018/028810
申请日：2018-04-23
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , HUSH, Glen E. , PINNEY, David L.
IPC分类号： G11C7/06 , G06F13/16
CPC分类号： G11C7/065 , G11C7/1006 , G11C7/1012 , G11C7/106 , G11C7/1087 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C2207/229 , G11C2211/4013
摘要： The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.

6. 发明申请

WO2016126474A1 APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE LOCATIONS 审中-公开
标题翻译：用于并行写入多个存储器件位置的装置和方法
公开(公告)号：WO2016126474A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015029
申请日：2016-01-27
申请人： MICRON TECHNOLOGY, INC.
发明人： ZAWODNY, Jason T. , HUSH, Glen E. , MANNING, Troy A. , FINKBEINER, Timothy P.
IPC分类号： G11C7/06 , G11C7/10 , G11C8/12
CPC分类号： G06F3/0611 , G06F3/0625 , G06F3/0659 , G06F3/0683 , G06F15/7821 , G11C5/025 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C29/28 , G11C2029/2602
摘要： The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
摘要翻译：本公开包括用于并行写入多个存储器设备位置的装置和方法。示例性设备包括存储器设备。存储器件包括耦合到阵列的存储器单元阵列和感测电路。感测电路包括读出放大器和被配置为实现逻辑运算的计算组件。存储器设备中的存储器控制器被配置为从主机接收解析的指令块和/或恒定数据。存储器控制器被配置为将解决的指令和/或常数数据并行地写入存储器件的多个位置。

7. 发明申请

WO2016036595A1 APPARATUSES AND METHODS FOR DETERMINING POPULATION COUNT 审中-公开
标题翻译：用于确定人口计数的装置和方法
公开(公告)号：WO2016036595A1
公开(公告)日：2016-03-10
申请号：PCT/US2015/047406
申请日：2015-08-28
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , HUSH, Glen E. , MURPHY, Richard C.
IPC分类号： G11C7/06 , G06F12/02
CPC分类号： G11C16/26 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1009 , G11C7/12
摘要： The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.
摘要翻译：本公开包括与确定人口数量有关的装置和方法。示例性设备包括耦合到感测电路的存储器单元的阵列。该装置可以包括：控制器，其被配置为：并行地对应于存储在阵列的存储器单元中的多个第一向量中的相应的数据值作为表示其总体计数的数据值和，其中第二向量被存储为多个第一向量，并且其中多个第一向量中的每个第一向量被存储在耦合到多个感测线的相应感测线的阵列的相应存储器单元中; 并且迭代地并行地求和与多个第一向量相对应的数据值和，以提供对应于第二向量的单个数据值。

8. 发明申请

WO2020077020A1 VECTOR REGISTERS IMPLEMENTED IN MEMORY 审中-公开
公开(公告)号：WO2020077020A1
公开(公告)日：2020-04-16
申请号：PCT/US2019/055487
申请日：2019-10-10
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , LARSEN, Troy D.
IPC分类号： G06F9/30 , G06F12/02
摘要： Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.

9. 发明申请

WO2020076831A1 COHERENT MEMORY ACCESS 审中-公开
公开(公告)号：WO2020076831A1
公开(公告)日：2020-04-16
申请号：PCT/US2019/055200
申请日：2019-10-08
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , LARSEN, Troy D.
IPC分类号： G06F12/0831 , G06F12/0844 , G06F12/0866 , G06F12/0875
摘要： Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

10. 发明申请

WO2019046032A1 PROCESSING IN MEMORY 审中-公开
公开(公告)号：WO2019046032A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/047172
申请日：2018-08-21
申请人： MICRON TECHNOLOGY, INC.
发明人： LEA, Perry V. , FINKBEINER, Timothy P.
IPC分类号： G06F13/16 , G06F3/06 , G11C7/06 , G11C7/22 , G11C11/4091 , G11C11/4076
摘要： Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

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