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1. 发明申请

WO2020076831A1 COHERENT MEMORY ACCESS 审中-公开
公开(公告)号：WO2020076831A1
公开(公告)日：2020-04-16
申请号：PCT/US2019/055200
申请日：2019-10-08
申请人： MICRON TECHNOLOGY, INC.
发明人： FINKBEINER, Timothy P. , LARSEN, Troy D.
IPC分类号： G06F12/0831 , G06F12/0844 , G06F12/0866 , G06F12/0875
摘要： Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

2. 发明申请

WO2023275632A1 MIRRORING DATA IN WRITE CACHES OF CONTROLLER OF NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2023275632A1
公开(公告)日：2023-01-05
申请号：PCT/IB2022/054831
申请日：2022-05-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
发明人： PLETKA, Roman , FISHER, Timothy , YANES, Adalberto , PAPANDREOU, Nikolaos , STOICA, Radu , POZIDIS, Charalampos , IOANNOU, Nikolas
IPC分类号： G06F12/08 , G06F12/0246 , G06F12/0844 , G06F12/0868 , G06F2212/72 , G06F2212/7201 , G06F2212/7203 , G06F3/0604 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0679
摘要： A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

3. 发明申请

WO2018146448A1 DATA PROCESSING 审中-公开
公开(公告)号：WO2018146448A1
公开(公告)日：2018-08-16
申请号：PCT/GB2018/050191
申请日：2018-01-23
申请人： ARM LIMITED
发明人： FILIPPO, Michael , JALAL, Jamshed , BRUCE, Klas Magnus , MEYER, Paul Gilbert , HAWKINS, David Joseph , MANNAVA, Phanindra Kumar , PUSDESRIS, Joseph Michael
IPC分类号： G06F12/0831 , G06F12/0844
摘要： A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

4. 发明申请

WO2017075372A1 ACCESSING CACHE 审中-公开
标题翻译：访问缓存
公开(公告)号：WO2017075372A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/059352
申请日：2016-10-28
申请人： ALIBABA GROUP HOLDING LIMITED
发明人： MA, Ling , WANG, Zhihong , ZHANG, Lei
IPC分类号： G06F12/0815 , G06F12/0844 , G06F12/0862
CPC分类号： G06F12/0862 , G06F12/0811 , G06F2212/283 , G06F2212/602 , Y02D10/13
摘要： A method for accessing a cache including reading an access instruction for acquiring data; determining, according to a delay identifier carried by the access instruction, whether the access instruction produces a delay; accessing the cache and performing, according to a location identifier carried by the access instruction, a pre-fetch operation if a delay is produced; and modifying, according to a location where the data required by the access instruction is acquired, the delay identifier and the location identifier carried by the access instruction. The technical solutions solve the problem of a low hit rate upon cache access, reduce the probability of misses, and reduce an access delay caused by a level-by-level access to each level of cache upon target data acquisition, which correspondingly lowers the power consumption generated upon the cache access and improves the CPU performance.
摘要翻译：一种用于访问高速缓存的方法，包括：读取用于获取数据的访问指令; 根据所述访问指令携带的延迟标识确定所述访问指令是否产生延迟; 访问高速缓存并根据访问指令所携带的位置标识符在产生延迟的情况下执行预取操作; 根据访问指令获取所需数据的位置，修改访问指令携带的延迟标识和位置标识。该技术方案解决了高速缓存访问时命中率较低的问题，降低了丢失概率，减少了在目标数据采集时逐级访问各级缓存所导致的访问延迟，相应地降低了功耗在缓存访问时产生的消耗并提高CPU性能。

5. 发明申请

WO2023033958A1 CRITICALITY-INFORMED CACHING POLICIES 审中-公开
公开(公告)号：WO2023033958A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/038712
申请日：2022-07-28
申请人： APPLE INC.
发明人： HUBERTY, Tyler J. , VENKATRAMAN, Vivek , GUPTA, Sandeep , FURBISH, Eric J. , SRIDHARAN, Srinivasa Rangan , MEIER, Stephan G.
IPC分类号： G06F9/38 , G06F9/30 , G06F12/0888 , G06F12/0844
摘要： A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

6. 发明申请

WO2022261200A1 MULTI-PLANE, MULTI-PROTOCOL MEMORY SWITCH FABRIC WITH CONFIGURABLE TRANSPORT 审中-公开
公开(公告)号：WO2022261200A1
公开(公告)日：2022-12-15
申请号：PCT/US2022/032664
申请日：2022-06-08
申请人： ENFABRICA CORPORATION
发明人： NORRIE, Thomas , MUKHERJEE, Shrijeet , GRETH, John , SANKAR, Rochan , MULLER, Shimon , HENDEL, Ariel , SINGH, Gurjeet
IPC分类号： G06F12/0802 , G06F12/084 , G06F12/0868 , G06F12/0844 , G06F12/0871 , G06F12/0873 , H04L49/356
摘要： A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.

7. 发明申请

WO2021122408A1 CACHE SNOOPING MODE EXTENDING COHERENCE PROTECTION FOR CERTAIN REQUESTS 审中-公开
公开(公告)号：WO2021122408A1
公开(公告)日：2021-06-24
申请号：PCT/EP2020/085894
申请日：2020-12-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED
发明人： WILLIAMS, Derek , GUTHRIE, Guy , SHEN, Hugh , MURRAY, Luke
IPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F12/0817 , G06F12/0831 , G06F12/0844 , G06F12/0855 , G06F12/0891 , G06F12/0828 , G06F12/0833 , G06F12/0842 , G06F12/0857
摘要： A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.

8. 发明申请

WO2019118016A1 MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION 审中-公开
公开(公告)号：WO2019118016A1
公开(公告)日：2019-06-20
申请号：PCT/US2018/048350
申请日：2018-08-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L. , JONES, William E.
IPC分类号： G06F12/0862 , G06F12/0844
摘要： A processing system (100) includes an interconnect fabric (110) coupleable to a local memory (112) and at least one compute complex (102) coupled to the interconnect fabric. The compute complex includes a processor core (114-117) and a cache hierarchy (118). The cache hierarchy has a plurality of caches (121-130) and a throttle controller (228) configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher (220) of a cache of the cache hierarchy.

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