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1. 发明申请

WO2008124444A1 METHODS TO FORM WIDE HEATER TRENCHES AND TO FORM MEMORY CELLS TO ENGAGE HEATERS 审中-公开
标题翻译：形成宽加热器的方法和形成记忆细胞进入加热器的方法
公开(公告)号：WO2008124444A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/059148
申请日：2008-04-02
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , WEI, Chien-Chuan , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , WEI, Chien-Chuan , LEE, Winston , LEE, Peter
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Embodiments of the present invention, provide a method that includes providing a wafer including multiple cells, each cell including at least one emitter (108), and performing a lithographic operation on the wafer. The lithographic operation comprises forming heater trenches adjacent the emitters, each heater trench having a width' that extends over at least respective portions of two cells. Embodiments of the present invention also provide a method that includes providing wafer including multiple cells, each cell including at least -one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element (402a, 402b) adjacent each emitter. Other embodiments are also described.
摘要翻译：本发明的实施例提供了一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极（108），并对所述晶片进行光刻操作。光刻操作包括在发射器附近形成加热器沟槽，每个加热器沟槽具有在两个单元的至少相应部分上延伸的宽度。本发明的实施例还提供了一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预先加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成与每个发射器相邻的加热器元件（402a，402b）。还描述了其它实施例。

2. 发明申请

WO2014066462A2 APPARATUS AND METHOD FOR REFORMING RESISTIVE MEMORY CELLS 审中-公开
标题翻译：用于改造电阻记忆细胞的装置和方法
公开(公告)号：WO2014066462A2
公开(公告)日：2014-05-01
申请号：PCT/US2013/066303
申请日：2013-10-23
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , LEE, Winston , LEE, Peter , CHANG, Runzi
发明人： SUTARDJA, Pantas , WU, Albert , LEE, Winston , LEE, Peter , CHANG, Runzi
IPC分类号： G11C29/50
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50008 , G11C2013/0076 , G11C2013/0083
摘要： A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.
摘要翻译：存储器包括存储器单元阵列，第一模块和第二模块。第一模块被配置为将存储器单元的第一状态与参考进行比较。存储单元位于存储单元的阵列中。第二模块被配置为在存储器单元的读取周期或写入周期之后并且基于该比较，改变存储器单元以调整存储器单元的第一状态和第二状态之间的差异。

3. 发明申请

WO2014062562A1 CONFIGURING RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY FOR WRITE OPERATIONS 审中-公开
标题翻译：配置电阻随机访问存储器（RRAM）阵列进行写操作
公开(公告)号：WO2014062562A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064819
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.
摘要翻译：系统包括电阻随机存取存储单元和驱动电路。电阻性随机存取存储单元包括电阻元件和开关元件，并且具有连接到位线的第一端子和连接到字线的第二端子。驱动器电路被配置为响应于使用字线选择电阻性随机存取存储器单元，将第一极性的第一电压施加到位线，以通过引起电流将电阻性随机存取存储器单元编程为第一状态沿着第一方向流过电阻元件，并向位线流过第二极性的第二电压，以通过使电流沿第二方向流过电阻元件而将电阻性随机存取存储器单元编程为第二状态。

4. 发明申请

WO2014062558A1 SYSTEMS AND METHODS FOR READING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS 审中-公开
标题翻译：用于读取电阻随机存取存储器（RRAM）的系统和方法
公开(公告)号：WO2014062558A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064811
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C11/16 , G11C13/00 , G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/1653 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0061
摘要： A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.
摘要翻译：一种包括连接到字线和位线的电阻性随机存取存储器单元的系统，以及配置成将该位线预充电到第一电压而未被选择的预充电电路。驱动器电路在位线被充电到第一电压之后的第一时间选择字线。比较器将位线上的第二电压与提供给比较器的第三电压进行比较，并根据比较产生输出。锁存器锁存比较器的输出并产生锁存输出。脉冲发生器在第一次之后的延迟之后产生脉冲以对时钟锁存器锁存比较器的输出并产生锁存的输出。锁存的输出表示电阻随机存取存储单元的状态。

5. 发明申请

WO2014062554A1 APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS 审中-公开
标题翻译：用于修复电阻记忆体的装置和方法，并增加感知放大器的整体读出灵敏度
公开(公告)号：WO2014062554A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/064801
申请日：2013-10-14
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
发明人： SUTARDJA, Pantas , WU, Albert , CHANG, Runzi , LEE, Winston , LEE, Peter
IPC分类号： G11C29/02
CPC分类号： G11C7/065 , G11C7/06 , G11C7/067 , G11C7/1057 , G11C7/106 , G11C11/1653 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C29/026
摘要： A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.
摘要翻译：存储器包括模块和解复用器。该模块配置为监视读出放大器的输出。读出放大器的每个输出被配置为处于第一状态或第二状态。该模块被配置为确定读出放大器的两个或多个输出处于相同状态。同样的状态是第一个状态或第二个状态。该模块被配置为输出读出放大器的两个或多个输出的状态。解复用器被配置为将读出放大器的两个或更多个输出的状态提供给锁存器。

6. 发明申请

WO2016196798A1 SYSTEMS AND METHODS FOR INCREASING PACKING DENSITY IN A SEMICONDUCTOR CELL ARRAY 审中-公开
标题翻译：在半导体细胞阵列中增加包装密度的系统和方法
公开(公告)号：WO2016196798A1
公开(公告)日：2016-12-08
申请号：PCT/US2016/035526
申请日：2016-06-02
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Sehat , LEE, Winston , LEE, Peter , CHANG, Runzi
发明人： SUTARDJA, Sehat , LEE, Winston , LEE, Peter , CHANG, Runzi
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/108
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L27/10802 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/16 , H01L29/456
摘要： Systems and methods are provided for using and manufacturing a semiconductor device. A semiconductor device comprises an array of transistors, wherein each respective transistor in at least some of the transistors in the array of transistors (i) is positioned adjacent to a respective first neighboring transistor and a respective second neighboring transistor in the array of transistors, (ii) has a source region that shares a first contact with a source region of the respective first neighboring transistor, and (iii) has a drain region that shares a second contact with a drain region of the respective second neighboring transistor.
摘要翻译：提供了使用和制造半导体器件的系统和方法。半导体器件包括晶体管阵列，其中晶体管阵列（i）中的至少一些晶体管中的每个相应的晶体管位于晶体管阵列中相应的第一相邻晶体管和相应的第二相邻晶体管附近（ ii）具有与相应的第一相邻晶体管的源极区域共享第一接触的源极区域，以及（iii）具有与相应的第二相邻晶体管的漏极区域共享第二接触的漏极区域。

7. 发明申请

WO2009100108A1 SYSTEM AND METHOD FOR DECODING A MEMORY ARRAY COMPRISING BLOCKS AND SUB-BLOCKS 审中-公开
标题翻译：用于解码包含块和子块的存储器阵列的系统和方法
公开(公告)号：WO2009100108A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/033040
申请日：2009-02-04
申请人： MARVELL WORLD TRADE LTD. , SUTARDJA, Pantas , LEE, Winston
发明人： SUTARDJA, Pantas , LEE, Winston
IPC分类号： G11C8/14 , G11C7/18 , G11C7/10
CPC分类号： G11C7/10 , G11C7/00 , G11C7/1006 , G11C7/18 , G11C8/12 , G11C8/14 , G11C2207/2209
摘要： A memory system includes Q memory blocks (216) that each include M memory sub-blocks (224). The memory system also includes Q word line decoders (206) that each are associated with a different one of the Q memory blocks (216). The memory system also includes a bit line decoder (309) and Q x M switch modules (319). Each Q x M switch module selectively controls access to one of the M memory sub-blocks of the Q memory blocks. The Q word line decoders and the bit line decoder access less than M memory sub-blocks in at least two of the Q memory blocks during one of a read and write operation. M and Q are integers greater than 1.
摘要翻译：存储器系统包括Q存储器块（216），每个存储器块包括M个存储器子块（224）。存储器系统还包括Q字线解码器（206），每个Q字线解码器都与Q存储器块（216）中的不同的一个相关联。存储器系统还包括位线解码器（309）和Q×M开关模块（319）。每个Q x M开关模块选择性地控制对Q存储器块的M个存储器子块之一的访问。在读取和写入操作期间，Q字线解码器和位线解码器在至少两个Q存储器块中访问少于M个存储器子块。 M和Q是大于1的整数。

8. 发明申请

WO2014074362A1 CONCURRENT USE OF SRAM CELLS WITH BOTH NMOS AND PMOS PASS GATES IN A MEMORY SYSTEM 审中-公开
标题翻译：在存储器系统中同时使用具有两个NMOS和PMOS门的SRAM单元
公开(公告)号：WO2014074362A1
公开(公告)日：2014-05-15
申请号：PCT/US2013/067454
申请日：2013-10-30
申请人： MARVELL WORLD TRADE LTD. , LEE, Winston , LEE, Peter
发明人： LEE, Winston , LEE, Peter
IPC分类号： G11C11/419 , G11C11/417 , G11C7/12
CPC分类号： G11C11/412 , G11C7/12 , G11C8/08 , G11C11/417 , G11C11/419
摘要： A memory system (290) includes first memory cells (292) and second memory cells (294). Each of the first memory cells (292) includes first and second pass gates including NMOS transistors. Each of the second memory cells (294) include first and second pass gates including PMOS transistors. The first memory cells (292) are pre- charged by one polarity (VDD) of a voltage supply. The second memory cells (294) are pre-charged by an opposite polarity (VSS) of the voltage supply. The invention also provides segmened word lines.
摘要翻译：存储器系统（290）包括第一存储单元（292）和第二存储单元（294）。每个第一存储单元（292）包括包括NMOS晶体管的第一和第二传递门。第二存储单元（294）中的每一个包括包括PMOS晶体管的第一和第二传递门。第一存储单元（292）由电压源的一个极性（VDD）预充电。第二存储单元（294）由电压源的相反极性（VSS）预充电。本发明还提供了分开的字线。

9. 发明申请

WO2014070852A1 SRAM CELLS SUITABLE FOR FIN FIELD-EFFECT TRANSISTOR (FINFET) PROCESS 审中-公开
标题翻译： SRAM CELLS适用于FIN场效应晶体管（FINFET）工艺
公开(公告)号：WO2014070852A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/067441
申请日：2013-10-30
申请人： MARVELL WORLD TRADE LTD. , LEE, Winston , LEE, Peter
发明人： LEE, Winston , LEE, Peter
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell includes first (220) and second (228) n-channel transistors, first (224) and second (232) p-channel transistors, first (234) and second (238) enable transistors, and first (208) and second (212) pass gates. The first n-channel transistor (220), the first p-channel transistor (224), and the first enable transistor (234) are connected in series between first (240) and second (236) reference potentials. The second n- channel transistor (228), the second p-channel transistor (232), and the second enable transistor (238) are connected in series between the first (240) and second (236) reference potentials. The first pass gate (208) is configured to selectively connect a first bitline (BL) to a first node. The first node is connected to a gate of the first n-channel transistor (220) and a gate of the first p-channel transistor (224). The second pass gate (212) is configured to selectively connect a second bitline (BLB) to a second node. The second node is connected to a gate of the second n-channel transistor (228) and a gate of the second p-channel transistor (232). The gate of the first (234) and second (238) enable transistors are respectively controlled by the first (BL) and second (BLB) bit lines so as to avoid conflict or competition between the first (224) and second (232) p-channel transistors and the first (208) and second (212) pass gates during a write operation. The present application further discloses word line repeaters and pulsed word line operation during reading.
摘要翻译：静态随机存取存储器（SRAM）单元包括第一（220）和第二（228）n沟道晶体管，第一（224）和第二（232）p沟道晶体管，第一（234）和第二（238）启用晶体管，以及第一（208）和第二（212）传输门。第一n沟道晶体管（220），第一p沟道晶体管（224）和第一启用晶体管（234）串联连接在第一（240）和第二（236）参考电位之间。第二n沟道晶体管（228），第二p沟道晶体管（232）和第二启用晶体管（238）串联连接在第一（240）和第二（236）参考电位之间。第一通过门（208）被配置为选择性地将第一位线（BL）连接到第一节点。第一节点连接到第一n沟道晶体管（220）的栅极和第一p沟道晶体管（224）的栅极。第二通过门（212）被配置为选择性地将第二位线（BLB）连接到第二节点。第二节点连接到第二n沟道晶体管（228）的栅极和第二p沟道晶体管（232）的栅极。第一（234）和第二（238）启用晶体管的栅极分别由第一（BL）和第二（BLB）位线控制，以避免第一（224）和第二（232）p之间的冲突或竞争（208）和第二（212）通道门电路。本申请进一步公开了在读取期间的字线转发器和脉冲字线操作。

10. 发明申请

WO2011071836A1 CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER 审中-公开
标题翻译：用于校正放大器偏移的电路和方法
公开(公告)号：WO2011071836A1
公开(公告)日：2011-06-16
申请号：PCT/US2010/059142
申请日：2010-12-06
申请人： MARVELL WORLD TRADE LTD , LEE, Winston , LEE, Peter
发明人： LEE, Winston , LEE, Peter
IPC分类号： H03F1/02
CPC分类号： H03F3/45179 , G11C7/06 , G11C7/062 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/2254 , H03F3/45475 , H03F3/45968 , H03F2203/45048 , H03F2203/45101 , H03F2203/45212 , H03F2203/45586 , H03F2203/45588 , H03F2203/45681
摘要： In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory.
摘要翻译：在一个实施例中，本公开包括一个电路，其包括具有输入和输出的放大器，偏移检测电路，用于检测放大器在放大器的输出处的偏移，以及偏移产生电路，其具有耦合到偏移的输入检测电路和耦合到放大器的输入端的输出端，以在放大器的运算阶段基于检测到的偏移量在放大器的输入处产生偏移。产生的偏移消除了放大器偏移的至少一部分。在一个实现中，放大器是存储器中的读出放大器。

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