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1. 发明申请

WO2012054201A1 WAFER TESTING SYSTEMS AND ASSOCIATED METHODS OF USE AND MANUFACTURE 审中-公开
标题翻译：测试系统和相关的使用和制造方法
公开(公告)号：WO2012054201A1
公开(公告)日：2012-04-26
申请号：PCT/US2011/053775
申请日：2011-09-28
申请人： ADVANCED INQUIRY SYSTEMS, INC. , DURBIN, Aaron , KEITH, David , JOHNSON, Morgan, T.
发明人： DURBIN, Aaron , KEITH, David , JOHNSON, Morgan, T.
IPC分类号： G01R31/20
CPC分类号： G01R1/07378 , G01R1/04 , G01R1/0408 , G01R1/0491 , G01R31/2601 , G01R31/2607 , G01R31/2886 , G01R31/2889
摘要： Wafer testing is disclosed. A wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.
摘要翻译：披露了晶圆测试。晶片测试系统包括用于通过单独可操作的真空或压力差将晶片可释放地附接到晶片转换器和晶片转换器到组件的组件。组件包括耦合到晶片转换器的晶片转换器支撑环，其中第一柔性材料从晶片转换器支撑环延伸，以便包围晶片转换器和插入器之间的空间，使得空间可以被第一真空抽真空通过一个或多个第一疏散路径。组件还可以包括耦合到晶片和卡盘的晶片支撑环，其中第二柔性材料从晶片支撑环延伸，以便包围晶片和晶片转换器之间的空间，使得空间可被第二个通过一个或多个第二排空路径进行真空。

2. 发明申请

WO2002064301A2 LASER MICROMACHINING AND ELECTRICAL STRUCTURES FORMED THEREBY 审中-公开
标题翻译：激光微型化和电气结构形成
公开(公告)号：WO2002064301A2
公开(公告)日：2002-08-22
申请号：PCT/US2002/004425
申请日：2002-02-12
申请人： JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： B23K26/00
CPC分类号： B23K26/073 , B23K26/382 , B23K26/40 , B23K2201/40 , B23K2203/12 , B23K2203/172 , B23K2203/42 , B23K2203/50 , H05K1/0269 , H05K1/0393 , H05K1/165 , H05K3/0032 , H05K3/0052 , H05K3/027 , H05K2201/09063 , H05K2201/0909 , H05K2201/09918
摘要： A unified process of making an electrical structure includes performing a plurality of laser etching operations on workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating subsrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and s ingulating the electrical structure. In another aspect of th einvention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wheein each plurality of etching operations is defined with respect to a common coordinate system.
摘要翻译：制造电结构的统一过程包括在工件上执行多个激光蚀刻操作，而不从激光处理系统移除工件。所述工件包括设置在电绝缘凹槽上的导电材料，并且所述多个激光蚀刻操作包括但不限于形成基准，形成由高纵横比空间分隔的厚金属迹线的两个或更多个，孔，切割折叠线以及对电气结构的进给。在本发明的另一方面，准备数据库，并且通信地耦合到激光处理系统，以提供控制信号，该控制信号指导激光处理系统的多个操作的一部分，每个多个蚀刻操作相对于一个共同的坐标系。

3. 发明申请

WO2008127541A1 FULLY TESTED WAFERS HAVING BOND PADS UNDAMAGED BY PROBING AND APPLICATIONS THEREOF 审中-公开
标题翻译：具有通过其探测和应用破坏的粘结垫的全部测试的波形
公开(公告)号：WO2008127541A1
公开(公告)日：2008-10-23
申请号：PCT/US2008/003858
申请日：2008-03-24
申请人： JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R1/073
CPC分类号： G01R31/2884 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products.
摘要翻译：用于生产完全被测试的非镶嵌集成电路的方法和装置，不对接合焊盘进行探针磨损损伤包括形成可移除地彼此附接的晶片/晶片转换器对，其中晶片转换器包括由软的可压电导电材料形成的接触结构，并且这些接触结构在惰性气体存在下与接合垫接触; 随后在晶片和晶片转换器之间抽真空。在本发明的一个方面中，由多个测试系统来执行无调制的集成电路，其中接合焊盘从未被测试系统物理地接触，并且仅通过晶片转换器的查询侧提供对晶片的电接触。在本发明的另一方面，提供了具有不具有探针擦洗痕的接合垫的已知的良好的模头用于结合到产品中。

4. 发明申请

WO2005018292A2 SELECTIVE APPLICATION OF CONDUCTIVE MATERIAL TO CIRCUIT BOARDS BY PICK AND PLACE 审中-公开
标题翻译：通过PICK和PLACE选择性地将导电材料应用于电路板
公开(公告)号：WO2005018292A2
公开(公告)日：2005-02-24
申请号：PCT/US2004/026503
申请日：2004-08-12
申请人： JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： H05K
CPC分类号： H05K3/4015 , H05K3/027 , H05K3/341 , H05K2203/0191 , H05K2203/0769 , H05K2203/0786 , Y10T428/12493 , Y10T428/12507 , Y10T428/12514
摘要： A component for use in manufacturing circuit boards, such as printed circuit boards, or flex substrates is adapted for use with pick-and-place equipment to provide a first material overlay disposed over a second material base layer. Such a component may include a first electrically conductive material disposed over a second electrically conductive material, and a soluble tape backing disposed over and attached to the second electrically conductive material. The component may be attached to a circuit board by solder relow, after which the soluble tape backing is removed. Although typical embodiments involve electrically conductive materials, it is noted that an electrically insulating material can also be disposed over and attached to an underlying material which itself is disposed on a circuit board.
摘要翻译：用于制造电路板（例如印刷电路板或柔性基板）的部件适于与拾取和放置设备一起使用以提供设置在第二材料基层上的第一材料覆盖层。这样的部件可以包括设置在第二导电材料上的第一导电材料和设置在第二导电材料上并附着到第二导电材料上的可溶性带背。组件可以通过焊料回流连接到电路板，然后除去可溶性胶带背衬。虽然典型的实施例涉及导电材料，但应注意的是，电绝缘材料也可以设置在本身设置在电路板上的下层材料上并附着于其上。

5. 发明申请

WO2008010919A3 METHODS AND APPARATUS FOR PLANAR EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE EDGES OF A SUBSTRATE 审中-公开
公开(公告)号：WO2008010919A3
公开(公告)日：2008-01-24
申请号：PCT/US2007/015529
申请日：2007-07-07
申请人： OCTAVIAN SCIENTIFIC, INC. , JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R31/02
摘要： Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

6. 发明申请

WO2007146291A2 METHOD AND APPARATUS FOR FIXED-FORM MULTI-PLANAR EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE MARGINS OF A SUBSTRATE 审中-公开
标题翻译：电子导体固定多平面延伸超过基板边界的方法和装置
公开(公告)号：WO2007146291A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/013788
申请日：2007-06-11
申请人： OCTAVIAN SCIENTIFIC, INC. , JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2851 , G01R31/2853 , G01R31/2855
摘要： An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.
摘要翻译：一种适于将晶片上的集成电路的焊盘与测试系统中的浮标塔的弹簧销耦合而不需要探针卡的装置包括具有第一表面和第二表面的本体，该主体具有基本上圆形中心部分和从中心部分向外延伸的多个可弯曲臂，每个可弯曲臂具有设置在其远端处的连接片; 设置在所述主体的中心部分的第二表面上的第一多个接触端子，所述第一多个接触端子以图案排列以匹配待接触的晶片上的焊盘的布局; 至少一个接触端子，设置在所述多个连接器接头的第一表面上; 以及设置在所述主体中的多个导电通路，使得所述第一多个接触端子中的每一个电连接到所述连接器接头的第一表面上的对应的一个接触端子。

7. 发明申请

WO2008011106A2 METHODS AND APPARATUS FOR FLEXIBLE EXTENSION OF ELECTRICAL CONDUCTORS BEYOND THE EDGES OF A SUBSTRATE 审中-公开
标题翻译：用于柔性延伸导线的方法和装置超出基板的边缘
公开(公告)号：WO2008011106A2
公开(公告)日：2008-01-24
申请号：PCT/US2007/016379
申请日：2007-07-18
申请人： OCTAVIAN SCIENTIFIC, INC. , JOHNSON, Morgan, T. , DECHER, Peter, H.
发明人： JOHNSON, Morgan, T. , DECHER, Peter, H.
IPC分类号： G01R31/02
CPC分类号： G01R31/2889
摘要： A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.
摘要翻译：柔性延伸晶片转换器包括晶片转换器部分，从其向外延伸的一个或多个柔性连接器以及连接到每个向外延伸的柔性连接器的远端的连接器接线片。柔性连接器可以采取任何合适的形式，包括但不限于覆盖和打褶。

8. 发明申请

WO2007123647A2 DESKTOP WAFER ANALYSIS STATION 审中-公开
标题翻译：桌面波分析站
公开(公告)号：WO2007123647A2
公开(公告)日：2007-11-01
申请号：PCT/US2007/007866
申请日：2007-03-28
申请人： JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R31/02
CPC分类号： G01R31/2831 , G01R31/2851
摘要： A small-footprint wafer analysis, or test, station, suitable for personal or desktop use, includes a chuck mounted upon a base, an x-y motion mechanism slidably attached to the base, a contact array carrier slidably attached to the x-y motion mechanism, and an optical alignment mechanism attached to the contact array carrier.
摘要翻译：适用于个人或桌面使用的小尺寸晶片分析或测试台包括安装在基座上的卡盘，可滑动地附接到基座的xy运动机构，可滑动地附接到xy运动机构的触点阵列载体，以及附接到接触阵列载体的光学对准机构。

9. 发明申请

WO2007145968A2 METHODS AND APPARATUS FOR MULTI-MODAL WAFER TESTING 审中-公开
标题翻译：多模式波形测试的方法和设备
公开(公告)号：WO2007145968A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/013274
申请日：2007-06-06
申请人： OCTAVIAN SCIENTIFIC, INC. , JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： G01R31/26
CPC分类号： G01R1/07342 , G01R31/2886
摘要： Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.
摘要翻译：通过使晶片和边缘延伸的晶片转换器进入附接状态来提供对晶片的集成电路的访问以同时执行两种或更多种类型的测试。边缘延伸晶片转换器具有设置在其上的晶片侧接触端子和询问侧接触端子，第一组晶片侧接触端子电耦合到第一组查询侧接触端子，以及第二组晶片侧接触端子电耦合到第二组询问侧接触端子。边缘延伸晶片转换器具有与附接的晶片大致共同延伸的中心部分，以及延伸超出通常由晶片的外圆周边缘限定的边界的边缘延伸部分。至少一个集成电路的第一组焊盘电耦合到第一组晶片侧接触端子，并且集成电路的第二组焊盘电耦合到第二组晶片侧接触端子。边缘延伸晶片转换器可以被成形为使得其边缘延伸部分不与其中心部分共面。

10. 发明申请

WO2004004076A1 ELECTRICAL CABLE INTERCONNECTIONS FOR REDUCED IMPEDANCE MISMATCHES 审中-公开
标题翻译：用于减少阻抗误差的电缆互连
公开(公告)号：WO2004004076A1
公开(公告)日：2004-01-08
申请号：PCT/US2003/020917
申请日：2003-07-01
申请人： JOHNSON, Morgan, T.
发明人： JOHNSON, Morgan, T.
IPC分类号： H01R12/00
CPC分类号： H01R24/50 , H01R2103/00
摘要： Reduced impedance mismatches are obtained when coupling electrical signalling media by replacing conventional connector architectures, which disrupt transmission line characteristics, with an electrical couling means that permits the electrical signalling media to present a planar interface for interconnection. A connector suitable for electrically coupling a first pair of coaxially arranged conductors (202) to a second pair of conductors (206) disposed on a substrate (204) includes a housing adapted to receive at least one coaxial cable having a planar interface, wherein the planar interface comprises a first conductor surface, a first dielectric surface, and a second conductor surface, the three surfaces being substantially coplanar with each other, and a connector bottom mechanically coupled to the housing and coupled to the planar coax cable interface, wherein the connector bottom comprises an electrically insulative portion having at least two major surfaces; and at least two electrically conductive portions.
摘要翻译：通过用允许电信令介质呈现用于互连的平面接口的电配置装置替代传统线路特性的传统连接器架构来代替传统的连接器架构来耦合电信令介质时，获得了减少的阻抗失配。适于将第一对同轴布置的导体（202）电耦合到设置在基板（204）上的第二对导体（206）的连接器包括适于容纳具有平面界面的至少一个同轴电缆的壳体，其中，平面界面包括第一导体表面，第一电介质表面和第二导体表面，所述三个表面彼此基本共面;以及连接器底部，其机械地联接到所述壳体并且耦合到所述平面同轴电缆接口，其中所述连接器底部包括具有至少两个主表面的电绝缘部分; 和至少两个导电部分。

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