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1. 发明申请

WO2006060575A3 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
公开(公告)号：WO2006060575A3
公开(公告)日：2006-06-08
申请号：PCT/US2005/043474
申请日：2005-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , ELLIS-MONAGHAN, John, J. , FANG, Sunfei , LAVOIE, Christian , LUO, Zhijiong , NAKOS, James, S. , STEEGEN, An, L. , WANN, Clement, H.
发明人： CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , ELLIS-MONAGHAN, John, J. , FANG, Sunfei , LAVOIE, Christian , LUO, Zhijiong , NAKOS, James, S. , STEEGEN, An, L. , WANN, Clement, H.
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/44
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

2. 发明申请

WO2006060574A2 METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 审中-公开
标题翻译：在CMOS器件中形成自对准的双完全硅化物门的方法
公开(公告)号：WO2006060574A2
公开(公告)日：2006-06-08
申请号：PCT/US2005/043473
申请日：2005-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
发明人： FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270），第一阱区（253）中的第一源极/漏极硅化物区域（266）和与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）。在所述半导体衬底（252）中形成具有第二阱区（254）的第二类型半导体器件（280），所述第二阱区（254）中的第二源极/漏极硅化物区域（256）和第二类型栅极（258））与第二源极/漏极硅化物区域（256）隔离; 选择性地在所述第二类型半导体器件（280）上形成第一金属层（218）; 仅在第二类型栅极（258）上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

3. 发明申请

WO2005083780A3 CMOS SILICIDE METAL GATE INTEGRATION 审中-公开
公开(公告)号：WO2005083780A3
公开(公告)日：2005-09-09
申请号：PCT/US2005/005565
申请日：2005-02-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , AMOS, Ricky, S. , BOYD, Diane, C. , CABRAL, Cyril, Jr. , KAPLAN, Richard, D. , KEDZIERSKI, Jakub, T. , KU, Victor , LEE, Woo-Hyeong , LI, Ying , MOCUTA, Anda, C. , NARAYANAN, Vijay , STEEGEN, An, L. , SURENDRA, Maheswaren
发明人： AMOS, Ricky, S. , BOYD, Diane, C. , CABRAL, Cyril, Jr. , KAPLAN, Richard, D. , KEDZIERSKI, Jakub, T. , KU, Victor , LEE, Woo-Hyeong , LI, Ying , MOCUTA, Anda, C. , NARAYANAN, Vijay , STEEGEN, An, L. , SURENDRA, Maheswaren
IPC分类号： H01L21/8238
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

4. 发明申请

WO2011064085A1 SELF ALIGNED CARBIDE SOURCE/DRAIN FET 审中-公开
标题翻译：自对准碳源/漏极FET
公开(公告)号：WO2011064085A1
公开(公告)日：2011-06-03
申请号：PCT/EP2010/066989
申请日：2010-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHANG, Josephine , GUILLORN, Michael , LAVOIE, Christian , CABRAL, Cyril, Jr. , GRILL, Alfred , O'SULLIVAN, Eugene
发明人： CHANG, Josephine , GUILLORN, Michael , LAVOIE, Christian , CABRAL, Cyril, Jr. , GRILL, Alfred , O'SULLIVAN, Eugene
IPC分类号： H01L29/775 , H01L29/16 , H01L51/05
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide drain portion, a nanostructure formed over the insulating carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物排出部分分离的绝缘碳部分，形成在绝缘碳部分上并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分和至少一部分纳米结构的至少一部分上的栅叠层。

5. 发明申请

WO2006080980A1 GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW 审中-公开
标题翻译：通过电化学处理利用栅极电介质电流流动的栅极堆叠工程
公开(公告)号：WO2006080980A1
公开(公告)日：2006-08-03
申请号：PCT/US2005/043466
申请日：2005-12-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , VEREECKEN, Philippe, M. , BASKER, Veeraraghavan , CABRAL, Cyril, Jr. , COOPER, Emanuel, I. , DELIGIANNI, Hariklia , FRANK, Martin, M. , JAMMY, Rajarao , PARUCHURI, Vamsi, Krishna , SAENGER, Katherine, L. , SHAO, Xiaoyan
发明人： VEREECKEN, Philippe, M. , BASKER, Veeraraghavan , CABRAL, Cyril, Jr. , COOPER, Emanuel, I. , DELIGIANNI, Hariklia , FRANK, Martin, M. , JAMMY, Rajarao , PARUCHURI, Vamsi, Krishna , SAENGER, Katherine, L. , SHAO, Xiaoyan
IPC分类号： H01L21/302 , H01L29/745
CPC分类号： H01L21/2885 , C25D3/50 , C25D5/02 , C25D5/024 , C25D5/54 , C25D7/123 , C25D9/04 , C25F3/14 , H01L21/28079 , H01L21/28114 , H01L21/76885 , H01L29/513 , H01L29/517 , H01L29/78648
摘要： A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.
摘要翻译：提供了一种在栅极电介质（2）上电镀栅极金属（9）或其它导电或半导体材料的方法。该方法包括选择衬底（3,4），电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许在电介质层之间的界面处产生电化学电流和电解质溶液或熔体。

6. 发明申请

WO2007112361A2 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 审中-公开
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：WO2007112361A2
公开(公告)日：2007-10-04
申请号：PCT/US2007/064946
申请日：2007-03-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , DELIGIANNI, Hariklia , KNARR, Randolph, F. , MALHOTRA, Sandra, G. , ROSSNAGEL, Stephen , SHAO, Xiaoyan , TOPOL, Anna , VEREECKEN, Philippe, M.
发明人： CABRAL, Cyril, Jr. , DELIGIANNI, Hariklia , KNARR, Randolph, F. , MALHOTRA, Sandra, G. , ROSSNAGEL, Stephen , SHAO, Xiaoyan , TOPOL, Anna , VEREECKEN, Philippe, M.
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a suicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the suicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的自杀或锗化物层，例如钴和/或镍; 接触层包括位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

7. 发明申请

WO2006055226A2 NITROGEN-CONTAINING FIELD EFFECT TRANSISTOR GATE STACK CONTAINING A THRESHOLD VOLTAGE CONTROL LAYER FORMED VIA DEPOSITION OF A METAL OXIDE 审中-公开
标题翻译：包含金属氧化物沉积形成的阈值电压控制层的含氮场效应晶体管栅格堆叠
公开(公告)号：WO2006055226A2
公开(公告)日：2006-05-26
申请号：PCT/US2005/039288
申请日：2005-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOJARCZUK, Nestor A., Jr. , CABRAL, Cyril, Jr. , CARTIER, Eduard A. , FRANK, Martin M. , GOUSEV, Evgeni P. , GUHA, Supratik , JAMISON, Paul C. , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi K.
发明人： BOJARCZUK, Nestor A., Jr. , CABRAL, Cyril, Jr. , CARTIER, Eduard A. , FRANK, Martin M. , GOUSEV, Evgeni P. , GUHA, Supratik , JAMISON, Paul C. , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi K.
IPC分类号： H01L29/94
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518
摘要： A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.
摘要翻译：提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。本发明还提供一种制造这种结构的方法。

8. 发明申请

WO2005062752A3 METAL CARBIDE GATE STRUCTURE AND METHOD OF FABRICATION 审中-公开
公开(公告)号：WO2005062752A3
公开(公告)日：2005-07-14
申请号：PCT/US2004/039855
申请日：2004-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , DETAVERNIER, Christopher , JAMMY, Rajarao , SAENGER, Katherine, L.
发明人： CABRAL, Cyril, Jr. , DETAVERNIER, Christopher , JAMMY, Rajarao , SAENGER, Katherine, L.
IPC分类号： H01L21/8238 , H01L29/76
摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET (210) that comprises a gate electrode (180) comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal (150) and a carbide of a metal.

9. 发明申请

WO2013039604A1 MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES 审中-公开
标题翻译：铜互连结构中的微结构修改
公开(公告)号：WO2013039604A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/047106
申请日：2012-07-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , NOGAMI, Takeshi , GAMBINO, Jeffrey, P. , HUANG, Qiang , RODBELL, Kenneth, P.
发明人： CABRAL, Cyril, Jr. , NOGAMI, Takeshi , GAMBINO, Jeffrey, P. , HUANG, Qiang , RODBELL, Kenneth, P.
IPC分类号： H01L21/28
CPC分类号： H01L21/7684 , H01L21/2885 , H01L21/76841 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L23/53233 , H01L23/53238 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90nm technologies. Preferably, bamboo grains are separated at distances less than the "Blech" length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.
摘要翻译：金属互连结构和金属互连结构的制造方法。为了在90nm以下的技术中，将锰（Mn）掺入到铜（Cu）互连结构中以改变微结构以实现竹型晶界。优选地，在小于“漂白”长度的距离处分离竹粒以避免通过晶界的铜（Cu）扩散。添加的Mn也触发Cu晶粒生长到金属线的底面，从而形成到达底面的真正的竹结构，消除沿金属线长度取向的晶界的Cu扩散机构。

10. 发明申请

WO2007011438A3 METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2007011438A3
公开(公告)日：2007-01-25
申请号：PCT/US2006/013173
申请日：2006-04-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , GORDON, Michael, S. , RODBELL, Kenneth, P.
发明人： CABRAL, Cyril, Jr. , GORDON, Michael, S. , RODBELL, Kenneth, P.
IPC分类号： H01L21/44
摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

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