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1. 发明申请

WO2008106244A3 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES 审中-公开
标题翻译： CMOS器件应变金属栅结构
公开(公告)号：WO2008106244A3
公开(公告)日：2010-03-18
申请号：PCT/US2008051067
申请日：2008-01-15
申请人： IBM , CHUDZIK MICHAEL P , HE WEI , MO RENEE T , MOUMEN NAIM , NARAYANAN VIJAY , PARK DAE-GYU , PARUCHURI VAMSI K
发明人： CHUDZIK MICHAEL P , HE WEI , MO RENEE T , MOUMEN NAIM , NARAYANAN VIJAY , PARK DAE-GYU , PARUCHURI VAMSI K
IPC分类号： H01L21/335
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底第一栅介质层。第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

2. 发明申请

WO2008132026A1 THRESHOLD ADJUSTMENT FOR HIGH-K GATE DIELECTRIC CMOS 审中-公开
标题翻译：用于高K栅介质CMOS的阈值调整
公开(公告)号：WO2008132026A1
公开(公告)日：2008-11-06
申请号：PCT/EP2008/054218
申请日：2008-04-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CARTIER, Eduard, Albert , DORIS, Bruce, Bennett , NARAYANAN, Vijay , PARUCHURI, Vamsi
发明人： CARTIER, Eduard, Albert , DORIS, Bruce, Bennett , NARAYANAN, Vijay , PARUCHURI, Vamsi
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823864 , H01L21/28176 , H01L27/092 , H01L29/6656 , Y10S438/981
摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner (22)'. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator (10) of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner (21). As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.
摘要翻译：公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫（22）'。该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体（10）。 CMOS结构的第二种类型的FET器件具有较厚的氧化物衬垫（21）。结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。本公开还教导了用于制造其中不同类型的FET器件具有不同厚度衬垫的CMOS结构的方法，并且不同类型的FET器件的阈值彼此独立地设置。

3. 发明申请

WO2008106244A2 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法
公开(公告)号：WO2008106244A2
公开(公告)日：2008-09-04
申请号：PCT/US2008/051067
申请日：2008-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHUDZIK, Michael, P. , HE, Wei , MO, Renee, T. , MOUMEN, Naim , NARAYANAN, Vijay , PARK, Dae-Gyu , PARUCHURI, Vamsi, K.
发明人： CHUDZIK, Michael, P. , HE, Wei , MO, Renee, T. , MOUMEN, Naim , NARAYANAN, Vijay , PARK, Dae-Gyu , PARUCHURI, Vamsi, K.
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底第一栅介质层。第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

4. 发明申请

WO2008098890A1 METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-K GATE DIELECTRIC STACKS 审中-公开
标题翻译：具有低电荷捕获的金属栅和增强的高K栅介质堆叠的电介质可靠性特性
公开(公告)号：WO2008098890A1
公开(公告)日：2008-08-21
申请号：PCT/EP2008/051595
申请日：2008-02-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ZAFAR, Sufi , CALLEGARI, Alessandro , CHUDZIK, Michael, Patrick , NARAYANAN, Vijay , PARUCHURI, Vamsi , LINDER, Barry, Paul , PARK, Dae-Gyu , MO, Renee, Tong
发明人： ZAFAR, Sufi , CALLEGARI, Alessandro , CHUDZIK, Michael, Patrick , NARAYANAN, Vijay , PARUCHURI, Vamsi , LINDER, Barry, Paul , PARK, Dae-Gyu , MO, Renee, Tong
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottomto top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositionalratioofmetal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio ofmetaland nitrogen within the sputter deposited layer.
摘要翻译：提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含氮金属层的底部至顶部。通过利用具有低于1.1的金属与氮的组成的金属含氮层来实现提高的可靠性。本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。本发明还提供一种制造这种栅极堆叠的方法，其中溅射工艺的工艺条件被改变以控制溅射沉积层内的金属和氮的比例。

5. 发明申请

WO2005104197A1 A METHOD OF FORMING A TANTALUM-CONTAINING GATE ELECTRODE STRUCTURE 审中-公开
标题翻译：一种形成含钛的电极结构的方法
公开(公告)号：WO2005104197A1
公开(公告)日：2005-11-03
申请号：PCT/US2005/004903
申请日：2005-02-15
申请人： TOKYO ELECTRON LIMITED , INTERNATIONAL BUSINESS MACHINES CORPORATION , NAKAMURA, Kazuhito , YAMASAKI, Hideaki , KAWANO, Yumiko , LEUSINK, Gert , MCFEELY, Fenton, R. , YURKAS, John, J. , NARAYANAN, Vijay
发明人： NAKAMURA, Kazuhito , YAMASAKI, Hideaki , KAWANO, Yumiko , LEUSINK, Gert , MCFEELY, Fenton, R. , YURKAS, John, J. , NARAYANAN, Vijay
IPC分类号： H01L21/28
CPC分类号： H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/51 , H01L29/517
摘要： A method for forming a tantalum-containing gate electrode structure (250, 260, 270) by providing a substrate (50, 252, 262, 272) having a high-k dielectric layer (254, 264, 274) thereon in a process chamber (1) and forming a tantalum-containing layer (256, 266, 276) on the high-k dielectric layer (254, 264, 274) in a thermal chemical vapor deposition process by exposing the substrate (50, 252, 262, 272) to a process gas containing TAIMATA (Ta(N(CH 3 ) 2 ) 3 (NC(C 2 H 5 )(CH 3 ) 2 )) precursor gas. In one embodiment of the invention, the tantalum-containing layer (256, 266,276) can include a TaSiN layer (256, 266, 276) formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer (278) is formed on the TaSiN layer (276). The TaN layer (278) can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium (1202, 1204, 1207, 1208) executable by a processor (1203) to cause a processing system (100, 220, 230) to perform the method and a processing system (100, 220, 230) for forming a tantalum-containing gate electrode structure (250, 260, 270) are also provided.
摘要翻译：一种通过在处理室中提供具有高k电介质层（254,264,274）的衬底（50,252,262,272）来形成含钽栅电极结构（250,260,270）的方法，（1），并且在热化学气相沉积工艺中在高k电介质层（254,264,274）上形成含钽层（256,266,276），通过使衬底（50,252,262,272）暴露）到含有TAIMATA（Ta（N（CH 3）2）3（NC（C 2 H 5）（CH 3）2））前体气体的工艺气体。在本发明的一个实施例中，含钽层（256,266,276）可以包括由含有TAIMATA前体气体，含硅气体和任选含氮的工艺气体形成的TaSiN层（256,266,276）加油站。在本发明的另一实施例中，在TaSiN层（276）上形成TaN层（278）。 TaN层（278）可以由含有TAIMATA前体气体和任选的含氮气体的工艺气体形成。一种可由处理器（1203）执行以使处理系统（100,220,230）执行所述方法的计算机可读介质（1202,1204,1207,1208）和用于形成所述处理系统的处理系统（100,220,230）还提供了含钽栅极电极结构（250,260,270）。

6. 发明申请

WO2005083780A3 CMOS SILICIDE METAL GATE INTEGRATION 审中-公开
公开(公告)号：WO2005083780A3
公开(公告)日：2005-09-09
申请号：PCT/US2005/005565
申请日：2005-02-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , AMOS, Ricky, S. , BOYD, Diane, C. , CABRAL, Cyril, Jr. , KAPLAN, Richard, D. , KEDZIERSKI, Jakub, T. , KU, Victor , LEE, Woo-Hyeong , LI, Ying , MOCUTA, Anda, C. , NARAYANAN, Vijay , STEEGEN, An, L. , SURENDRA, Maheswaren
发明人： AMOS, Ricky, S. , BOYD, Diane, C. , CABRAL, Cyril, Jr. , KAPLAN, Richard, D. , KEDZIERSKI, Jakub, T. , KU, Victor , LEE, Woo-Hyeong , LI, Ying , MOCUTA, Anda, C. , NARAYANAN, Vijay , STEEGEN, An, L. , SURENDRA, Maheswaren
IPC分类号： H01L21/8238
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

7. 发明申请

WO2012121852A1 LARGE-GRAIN, LOW-RESISTIVITY TUNGSTEN ON A CONDUCTIVE COMPOUND 审中-公开
标题翻译：大颗粒，导电性化合物的低电阻率TUNGSTEN
公开(公告)号：WO2012121852A1
公开(公告)日：2012-09-13
申请号：PCT/US2012/025411
申请日：2012-02-16
申请人： INTERNATIONAL BUSINESS MACHINES CORP. , BROWN, Stephen L. , BRULEY, John , CABRAL JR., Cyril , CALLEGARI, Sandro , FRANK, Martin M. , GUILLORN, Michael A. , HOPSTAKEN, Marinus , NARAYANAN, Vijay , KWONG HON WONG, Keith
发明人： BROWN, Stephen L. , BRULEY, John , CABRAL JR., Cyril , CALLEGARI, Sandro , FRANK, Martin M. , GUILLORN, Michael A. , HOPSTAKEN, Marinus , NARAYANAN, Vijay , KWONG HON WONG, Keith
IPC分类号： H01L21/70 , C23C14/06 , H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L23/53266 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.
摘要翻译：层状结构和半导体器件以及用于制造层状结构和半导体器件的方法。层状结构包括：包含含有氮化钛，氮化钽或其组合的材料的基底层; 包括含有氮化铝钽，氮化铝钛，氮化硅，氮化钛，氮化钽，氮化钛，氮化铪，碳化铪，碳化钽，氮化钒，氮化铌或其组合的材料的导电层物; 和钨层。半导体器件包括：半导体衬底; 基层; 导电层; 和钨层。

8. 发明申请

WO2012099928A2 STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES 审中-公开
标题翻译：用于降低高K金属栅器件中VT-W效应的结构和方法
公开(公告)号：WO2012099928A2
公开(公告)日：2012-07-26
申请号：PCT/US2012021664
申请日：2012-01-18
申请人： IBM , AQUILINO MICHAEL V , BAIOCCO CHRISTOPHER V , CONTI RICHARD A , JAEGER DANIEL J , NARAYANAN VIJAY
发明人： AQUILINO MICHAEL V , BAIOCCO CHRISTOPHER V , CONTI RICHARD A , JAEGER DANIEL J , NARAYANAN VIJAY
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/76229 , H01L29/517
摘要： A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.
摘要翻译：提供衬底。 STI沟槽形成在衬底中。填充材料形成在STI沟槽中，然后平坦化。衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。衬垫可降低高k金属栅极器件中的Vt-W效应。

9. 发明申请

WO2011157487A1 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS 审中-公开
标题翻译：外延源/漏极联系人自定义为沉积FET通道的栅极
公开(公告)号：WO2011157487A1
公开(公告)日：2011-12-22
申请号：PCT/EP2011/057455
申请日：2011-05-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHANG, Josephine , CHANG, Paul , NARAYANAN, Vijay , SLEIGHT, Jeffrey
发明人： CHANG, Josephine , CHANG, Paul , NARAYANAN, Vijay , SLEIGHT, Jeffrey
IPC分类号： H01L51/05 , H01L51/00
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，形成栅极电介质和栅电极栅叠层 CNT，同时保持其结构完整性，并且形成外延源极和漏极区域，其与晶体介质衬底上从栅极电介质层和栅电极栅极叠层露出的部分CNT接触。

10. 发明申请

WO2007050312A3 LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS 审中-公开
公开(公告)号：WO2007050312A3
公开(公告)日：2007-05-03
申请号：PCT/US2006/039940
申请日：2006-10-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CARTER, Eduard, A. , COPEL, Matthew, W. , FRANK, Martin, M. , GOUSEV, Evgeni, P. , JAMISON, Paul, C. , JAMMY, Rajarao , LINDER, Barry, P. , NARAYANAN, Vijay
发明人： CARTER, Eduard, A. , COPEL, Matthew, W. , FRANK, Martin, M. , GOUSEV, Evgeni, P. , JAMISON, Paul, C. , JAMMY, Rajarao , LINDER, Barry, P. , NARAYANAN, Vijay
IPC分类号： H01L29/76
摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO 2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

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