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1. 发明申请

WO2006060575A3 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
公开(公告)号：WO2006060575A3
公开(公告)日：2006-06-08
申请号：PCT/US2005/043474
申请日：2005-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , ELLIS-MONAGHAN, John, J. , FANG, Sunfei , LAVOIE, Christian , LUO, Zhijiong , NAKOS, James, S. , STEEGEN, An, L. , WANN, Clement, H.
发明人： CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , ELLIS-MONAGHAN, John, J. , FANG, Sunfei , LAVOIE, Christian , LUO, Zhijiong , NAKOS, James, S. , STEEGEN, An, L. , WANN, Clement, H.
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/44
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

2. 发明申请

WO2006060574A2 METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS DEVICES 审中-公开
标题翻译：在CMOS器件中形成自对准的双完全硅化物门的方法
公开(公告)号：WO2006060574A2
公开(公告)日：2006-06-08
申请号：PCT/US2005/043473
申请日：2005-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
发明人： FANG, Sunfei , CABRAL, Cyril, Jr. , DZIOBKOWSKI, Chester, T. , LAVOIE, Christian , WANN, Clement, H.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835
摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).
摘要翻译：一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270），第一阱区（253）中的第一源极/漏极硅化物区域（266）和与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）。在所述半导体衬底（252）中形成具有第二阱区（254）的第二类型半导体器件（280），所述第二阱区（254）中的第二源极/漏极硅化物区域（256）和第二类型栅极（258））与第二源极/漏极硅化物区域（256）隔离; 选择性地在所述第二类型半导体器件（280）上形成第一金属层（218）; 仅在第二类型栅极（258）上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

3. 发明申请

WO2007140288A2 FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 审中-公开
标题翻译：使用块状半导体波形形成改进的SOI衬底
公开(公告)号：WO2007140288A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069720
申请日：2007-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , HENSON, William, K. , NG, Hung, Y. , RIM, Kern , WANN, Clement, H.
发明人： CHIDAMBARRAO, Dureseti , HENSON, William, K. , NG, Hung, Y. , RIM, Kern , WANN, Clement, H.
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions (2, 4, 6). Each device region comprises at least a base semiconductor substrate layer (12) and a semiconductor device layer (16) with a buried insulator layer (14) located therebetween, while the semiconductor device layer (16) is supported by one or more vertical insulating pillars (22). The vertical insulating pillars (22) each preferably has a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by one or more vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).
摘要翻译：本发明涉及具有一个或多个器件区域（2,4,6）的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层（12）和半导体器件层（16），其中位于其间的掩埋绝缘体层（14），而半导体器件层（16）由一个或多个垂直绝缘柱（22）。垂直绝缘柱（22）各自优选地具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由一个或多个垂直绝缘体柱（22）。气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

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