专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011066035A3 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：用于降低谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：WO2011066035A3
公开(公告)日：2011-07-28
申请号：PCT/US2010050805
申请日：2010-09-30
申请人： IBM , BOTULA ALAN B , ELLIS-MONAGHAN JOHN J , JOSEPH ALVIN J , LEVY MAX G , PHELPS RICHARD A , SLINKMAN JAMES A
发明人： BOTULA ALAN B , ELLIS-MONAGHAN JOHN J , JOSEPH ALVIN J , LEVY MAX G , PHELPS RICHARD A , SLINKMAN JAMES A
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）位于绝缘体层上的半导体结构（100）。衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。此外，紧邻绝缘体层的半导体衬底的一部分（102）可以用稍高剂量的相同掺杂剂（111），具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加以及电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了任何得到的寄生电容器的阈值电压（Vt），从而降低了谐波行为。在此还公开了用于这种半导体结构的方法和设计结构的实施例。

2. 发明申请

WO2012047509A3 PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE 审中-公开
标题翻译：用于泄漏消除的带有保持节点的像素传感器单元及其制造和设计结构的方法
公开(公告)号：WO2012047509A3
公开(公告)日：2012-05-31
申请号：PCT/US2011052436
申请日：2011-09-21
申请人： IBM , ADKISSON JAMES W , ELLIS-MONAGHAN JOHN J , RASSEL RICHARD J
发明人： ADKISSON JAMES W , ELLIS-MONAGHAN JOHN J , RASSEL RICHARD J
IPC分类号： H04N5/357 , H01L27/146 , H04N5/359 , H04N5/361 , H04N5/376
CPC分类号： H04N5/3595 , H01L27/14603 , H01L27/14609 , H04N5/3532 , H04N5/359 , H04N5/3745 , H04N5/378
摘要： A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided., A pixel array includes one or more reference pixel sensor ceils (5') dispersed locally throughout active light sensing regions (5). The one or more reference pixel sensor cells provides reference signal (Vdd or REFERENCE) used, to correct for photon generated leakage signals which vary by locality within the active light sensing regions.
摘要翻译：提供了具有用于泄漏消除的保持节点，制造方法和设计结构的参考像素传感器单元（例如，全局快门），A像素阵列包括在主动光感测区域局部分散的一个或多个参考像素传感器细胞（5'）（5）。一个或多个参考像素传感器单元提供使用的参考信号（Vdd或REFERENCE），以校正由有源光感测区域内的位置变化的光子产生的泄漏信号。

3. 发明申请

WO2009012295A3 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 审中-公开
标题翻译：融合源/漏硅化物的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：WO2009012295A3
公开(公告)日：2009-03-12
申请号：PCT/US2008070143
申请日：2008-07-16
申请人： IBM , ANDERSON BRENT A , BRYANT ANDRES , ELLIS-MONAGHAN JOHN J , NOWAK EDWARD J
发明人： ANDERSON BRENT A , BRYANT ANDRES , ELLIS-MONAGHAN JOHN J , NOWAK EDWARD J
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：本文公开了多个鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍片部分地或完全地由高导电材料（360a，360b）（例如金属硅化物）合并。以这种方式合并鳍片允许串联电阻最小化，而栅极和源极/漏极区域（375a-b）之间的寄生电容几乎没有增加（如果有的话）。以这种方式合并半导体鳍（350）还允许每个源极/漏极区（375a-b）通过单个接触通孔接触，以及该接触通孔更灵活的放置。

4. 发明申请

WO2006060575A2 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：WO2006060575A2
公开(公告)日：2006-06-08
申请号：PCT/US2005043474
申请日：2005-12-01
申请人： IBM , CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , ELLIS-MONAGHAN JOHN J , FANG SUNFEI , LAVOIE CHRISTIAN , LUO ZHIJIONG , NAKOS JAMES S , STEEGEN AN L , WANN CLEMENT H
发明人： CABRAL CYRIL JR , DZIOBKOWSKI CHESTER T , ELLIS-MONAGHAN JOHN J , FANG SUNFEI , LAVOIE CHRISTIAN , LUO ZHIJIONG , NAKOS JAMES S , STEEGEN AN L , WANN CLEMENT H
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

5. 发明申请

WO2009140099A2 METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 审中-公开
标题翻译：用于形成CMOS图像传感器的抗反射结构的方法
公开(公告)号：WO2009140099A2
公开(公告)日：2009-11-19
申请号：PCT/US2009/042766
申请日：2009-05-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ADKISSON, James, W. , ELLIS-MONAGHAN, John, J. , GAMBINO, Jeffrey, P. , MUSANTE, Charles, F.
发明人： ADKISSON, James, W. , ELLIS-MONAGHAN, John, J. , GAMBINO, Jeffrey, P. , MUSANTE, Charles, F.
IPC分类号： H01L31/18 , H01L31/0236
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

6. 发明申请

WO2006081012A1 DUAL SILICIDE PROCESS TO IMPROVE DEVICE PERFORMANCE 审中-公开
标题翻译：双硅工艺提高器件性能
公开(公告)号：WO2006081012A1
公开(公告)日：2006-08-03
申请号：PCT/US2005/046097
申请日：2005-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELLIS-MONAGHAN, John, J. , MARTIN, Dale, W. , MURPHY, William, J. , NAKOS, James, S. , PETERSON, Kirk
发明人： ELLIS-MONAGHAN, John, J. , MARTIN, Dale, W. , MURPHY, William, J. , NAKOS, James, S. , PETERSON, Kirk
IPC分类号： H01L21/8238 , H01L29/772 , H01L29/78
CPC分类号： H01L29/7845 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/4933 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region (20) and a n-type device region (10); a first-type silicide contact (30) to the n-type device region (10); the first-type silicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact (35) to the p-type device region (20); the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.
摘要翻译：半导体结构及其形成方法包括具有p型器件区（20）和n型器件区（10）的衬底; 向所述n型器件区域（10）提供第一型硅化物接触（30）; 所述第一型硅化物具有基本上与所述n型器件区域导带对准的功函数; 和与p型器件区域（20）的第二类型硅化物接触（35）。所述第二类型硅化物具有基本上对准所述p型器件区域价带的功函数。本发明还提供了半导体结构及其形成方法，其中选择硅化物接触材料和硅化物接触处理条件以在pFET和nFET器件中提供基于应变的器件改进。

7. 发明申请

WO2012047509A2 PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE 审中-公开
标题翻译：具有保护节点的PIXEL传感器用于泄漏消除以及制造和设计结构的方法
公开(公告)号：WO2012047509A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/052436
申请日：2011-09-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ADKISSON, James W. , ELLIS-MONAGHAN, John J. , RASSEL, Richard J.
发明人： ADKISSON, James W. , ELLIS-MONAGHAN, John J. , RASSEL, Richard J.
IPC分类号： H04N5/357 , H04N5/359 , H04N5/376 , H04N5/361 , H01L27/146
CPC分类号： H04N5/3595 , H01L27/14603 , H01L27/14609 , H04N5/3532 , H04N5/359 , H04N5/3745 , H04N5/378
摘要： A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided., A pixel array includes one or more reference pixel sensor ceils (5') dispersed locally throughout active light sensing regions (5). The one or more reference pixel sensor cells provides reference signal (Vdd or REFERENCE) used, to correct for photon generated leakage signals which vary by locality within the active light sensing regions.
摘要翻译：提供了具有用于泄漏消除的保持节点的参考像素传感器单元（例如，全局快门），制造方法和设计结构。像素阵列包括一个或多个参考像素传感器单元（5' ）局部分散在整个有源光感测区域（5）中。一个或多个参考像素传感器单元提供所使用的参考信号（Vdd或参考），以校正因有源光感测区域内的局部性而变化的光子产生的泄漏信号。

8. 发明申请

WO2011066035A2 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
标题翻译：用于减少谐波的硅绝缘体（SOI）结构，设计结构和方法
公开(公告)号：WO2011066035A2
公开(公告)日：2011-06-03
申请号：PCT/US2010/050805
申请日：2010-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOTULA, Alan, B. , ELLIS-MONAGHAN, John, J. , JOSEPH, Alvin, J. , LEVY, Max, G. , PHELPS, Richard, A. , SLINKMAN, James, A.
发明人： BOTULA, Alan, B. , ELLIS-MONAGHAN, John, J. , JOSEPH, Alvin, J. , LEVY, Max, G. , PHELPS, Richard, A. , SLINKMAN, James, A.
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）在绝缘体层上的半导体结构（100）。衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。此外，紧邻绝缘体层的半导体衬底的一部分（102）可掺杂相同掺杂剂（111）的略高的剂量，具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了所得到的寄生电容器的阈值电压（Vt），从而降低了谐波特性。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

9. 发明申请

WO2009140099A3 METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 审中-公开
标题翻译：用于形成CMOS图像传感器的抗反射结构的方法
公开(公告)号：WO2009140099A3
公开(公告)日：2010-01-21
申请号：PCT/US2009042766
申请日：2009-05-05
申请人： IBM , ADKISSON JAMES W , ELLIS-MONAGHAN JOHN J , GAMBINO JEFFREY P , MUSANTE CHARLES F
发明人： ADKISSON JAMES W , ELLIS-MONAGHAN JOHN J , GAMBINO JEFFREY P , MUSANTE CHARLES F
IPC分类号： H01L31/112
CPC分类号： H01L27/14685 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14689 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.
摘要翻译：具有小于由光电二极管（8）可检测的光的波长范围的垂直（h）和横向（p）尺寸的凸起（5）形成在具有不同折射率的两个层之间的光学界面处。突起可以通过使用在第二聚合物嵌段组分（111）的基体内形成第一聚合物嵌段组分（112）的亚光刻特征阵列的自组装嵌段共聚物来形成。聚合物嵌段组分的图案被转移到第一光学层（4）中以形成纳米级突起的阵列。或者，可以使用常规光刻来形成尺寸小于光的波长的突起。第二光学层直接形成在第一光学层的突起上。第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

10. 发明申请

WO2009012295A2 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 审中-公开
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：WO2009012295A2
公开(公告)日：2009-01-22
申请号：PCT/US2008/070143
申请日：2008-07-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , ELLIS-MONAGHAN, John, J. , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , ELLIS-MONAGHAN, John, J. , NOWAK, Edward, J.
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍部分或完全地部分由高导电性材料（360a，360b）（例如，金属硅化物）合并。以这种方式合并散热片允许串联电阻最小化，栅极和源极/漏极区域（375a-b）之间的寄生电容几乎不增加（如果有的话）。以这种方式合并半导体散热片（350）还允许源极/漏极区域（375a-b）中的每一个被单个接触通孔接触以及该接触通孔的更灵活的放置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式