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1. 发明申请

WO2013002884A1 6F2 DRAM CELL 审中-公开
公开(公告)号：WO2013002884A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/034431
申请日：2012-04-20
申请人： INTEL CORPORATION , WANG, Yih , WEBB, M. Clair , LINDERT, Nick , SIVAKUMAR, Swaminathan , ZHANG, Kevin X. , SOMASEKHAR, Dinesh
发明人： WANG, Yih , WEBB, M. Clair , LINDERT, Nick , SIVAKUMAR, Swaminathan , ZHANG, Kevin X. , SOMASEKHAR, Dinesh
IPC分类号： G11C5/02 , G11C5/06 , G11C11/40 , H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10891
摘要： A 6F 2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
摘要翻译：描述了具有成对单元的6F2 DRAM单元。在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。虚拟字线由具有有利于p沟道器件的功函数的金属制成。

2. 发明申请

WO2010039629A2 METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY 审中-公开
标题翻译：在扩展特征的垂直侧壁上图案化金属的方法，使用该方法形成嵌入式MIM电容器的方法以及由此制造的嵌入式存储器装置
公开(公告)号：WO2010039629A2
公开(公告)日：2010-04-08
申请号：PCT/US2009/058540
申请日：2009-09-28
申请人： INTEL CORPORATION , KEATING, Steven J. , LINDERT, Nick , RAHHAL-ORABI, Nadia , DOYLE, Brian , SURI, Satyarth , SIVAKUMAR, Swaminathan , JONG, Lana , SHA, Lin
发明人： KEATING, Steven J. , LINDERT, Nick , RAHHAL-ORABI, Nadia , DOYLE, Brian , SURI, Satyarth , SIVAKUMAR, Swaminathan , JONG, Lana , SHA, Lin
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/027
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译：一种在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）在挖掘的特征中，使得金属的一部分（435）暴露在材料上方的挖掘特征中，使用第一湿法蚀刻化学物质蚀刻远离垂直侧壁的金属的暴露部分，并从挖掘出的材料中去除材料通过使用第二湿法蚀刻化学物质将其蚀刻掉。所描述的方法可以用于制造适用于eDRAM器件的MIM电容器（800）。

3. 发明申请

WO2013101107A1 DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES 审中-公开
标题翻译：双重图案平铺技术
公开(公告)号：WO2013101107A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067929
申请日：2011-12-29
申请人： INTEL CORPORATION , WALLACE, Charles H. , SIVAKUMAR, Swaminathan , TINGEY, Matthew L. , MUNASINGHE, Chanaka D. , RAHHAL-ORABI, Nadia M.
发明人： WALLACE, Charles H. , SIVAKUMAR, Swaminathan , TINGEY, Matthew L. , MUNASINGHE, Chanaka D. , RAHHAL-ORABI, Nadia M.
IPC分类号： H01L21/027
CPC分类号： H01L21/3088 , H01L21/0337
摘要： Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.
摘要翻译：公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸通过光刻工艺在衬底或其它合适的表面中形成的几何特征。在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。

4. 发明申请

WO2013095548A1 GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME 审中-公开
标题翻译：门对齐接触件和方法制作
公开(公告)号：WO2013095548A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066989
申请日：2011-12-22
申请人： INTEL CORPORATION , GOLONZKA, Oleg , SIVAKUMAR, Swaminathan , WALLACE, Charles, H. , GHANI, Tahir
发明人： GOLONZKA, Oleg , SIVAKUMAR, Swaminathan , WALLACE, Charles, H. , GHANI, Tahir
IPC分类号： H01L21/28 , H01L21/3205 , H01L29/78 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28008 , H01L21/30625 , H01L21/32 , H01L21/76805 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L29/0653 , H01L29/66545
摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
摘要翻译：描述门对齐的触点和形成栅极对准触点的方法。例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。在形成多个接触插塞之后形成多个触点和多个栅极结构。

5. 发明申请

WO2018118092A1 ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES 审中-公开
公开(公告)号：WO2018118092A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068586
申请日：2016-12-23
申请人： INTEL CORPORATION , SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
发明人： SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
IPC分类号： H01L21/768 , H01L21/027
摘要： Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

6. 发明申请

WO2013101108A1 PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES 审中-公开
标题翻译：图案分解光刻技术
公开(公告)号：WO2013101108A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067930
申请日：2011-12-29
申请人： INTEL CORPORATION , WALLACE, Charles H. , ABDALLAH, Hossam M. , TAN, Elliot N. , SIVAKUMAR, Swaminathan , GOLONZKA, Oleg , BIGWOOD, Robert M.
发明人： WALLACE, Charles H. , ABDALLAH, Hossam M. , TAN, Elliot N. , SIVAKUMAR, Swaminathan , GOLONZKA, Oleg , BIGWOOD, Robert M.
IPC分类号： H01L21/027
CPC分类号： H01L24/09 , G03F1/50 , G03F1/70 , G03F7/0035 , G03F7/16 , G03F7/40 , G03F7/70741 , H01L21/02345 , H01L21/0273 , H01L21/2633 , H01L21/30604 , H01L21/3086 , H01L27/0207 , H01L2224/0801 , H01L2224/08053 , H01L2224/0912 , H01L2924/14
摘要： Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.
摘要翻译：公开了用于通过将其分解（分解）成多个单向目标特征来实现二维目标光刻特征/图案的技术，其在聚合时基本上（例如，完全）代表原始目标特征而不留下未表示的余数（例如，全数量的单向目标特征）。单向目标特征可以被任意分组，使得在分组内，所有单向目标特征共享共同的目标宽度值。在提供多个这样的分组的情况下，个体分组可以具有或不具有相同的共同目标宽度值。在一些情况下，提供一系列光罩，每个掩模版具有与单向目标特征的分组相关的掩模图案。基本上（例如，完全）通过聚集的标线系列曝光光致抗蚀剂材料产生原始目标特征/图案。图案分解技术可以集成到任何数量的图案化工艺中，例如光刻冷冻 - 光刻蚀刻和光蚀刻 - 光蚀刻图案化工艺。

7. 发明申请

WO2009085520A2 TRANSISTOR HAVING RAISED SOURCE/DRAIN SELF-ALIGNED CONTACTS AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有上升源/排水自对准接触器的晶体管及其形成方法
公开(公告)号：WO2009085520A2
公开(公告)日：2009-07-09
申请号：PCT/US2008/084947
申请日：2008-11-26
申请人： INTEL CORPORATION , SIVAKUMAR, Swaminathan
发明人： SIVAKUMAR, Swaminathan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/76897 , H01L29/66628 , H01L29/66659
摘要： A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.
摘要翻译：晶体管结构及其形成方法。晶体管结构包括：具有栅极侧表面的半导体衬底; 设置在所述栅极侧表面上的栅极，所述栅极在所述栅极侧表面上延伸第一高度; 半导体延伸部，其设置在所述栅极侧表面上并且在所述栅极侧表面上方延伸高于所述第一高度的第二高度，所述半导体延伸部包括具有位于所述第二高度的扩散表面的扩散区域; 以及电耦合到扩散表面的扩散接触元件。

8. 发明申请

WO2017044106A1 SELF-ALIGNED ISOTROPIC ETCH OF PRE-FORMED VIAS AND PLUGS FOR BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
标题翻译：自动对准的预制六角形等离子体蚀刻线和后端（BEOL）互连线
公开(公告)号：WO2017044106A1
公开(公告)日：2017-03-16
申请号：PCT/US2015/049498
申请日：2015-09-10
申请人： INTEL CORPORATION , WALLACE, Charles H. , SIVAKUMAR, Swaminathan
发明人： WALLACE, Charles H. , SIVAKUMAR, Swaminathan , TAN, Elliot N. , NYHUS, Paul A.
IPC分类号： H01L21/027
CPC分类号： H01L21/76802 , H01L21/0337 , H01L21/31111 , H01L21/76801 , H01L21/76816 , H01L21/76879 , H01L21/76897
摘要： Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
摘要翻译：描述了用于后端（BEOL）互连的通孔和插图图案的自对准各向同性蚀刻工艺，以及所得到的结构。在一个示例中，制造用于集成电路的互连结构的方法包括通过图案化层中的开口去除多个孔或沟槽的子集的牺牲或永久占位符材料。该方法还包括去除图案层并用永久材料填充多个孔或沟槽的子集。

9. 发明申请

WO2013101202A1 TECHNIQUES FOR PHASE TUNING FOR PROCESS OPTIMIZATION 审中-公开
标题翻译：用于过程优化的相位调整技术
公开(公告)号：WO2013101202A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068157
申请日：2011-12-30
申请人： INTEL CORPORATION , NYHUS, Paul A. , OGADHOH, Shem O. , SIVAKUMAR, Swaminathan , JEONG, Seongtae
发明人： NYHUS, Paul A. , OGADHOH, Shem O. , SIVAKUMAR, Swaminathan , JEONG, Seongtae
IPC分类号： H01L21/027 , G03F1/36
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译：提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。

10. 发明申请

WO2013101105A1 SPACER ASSISTED PITCH DIVISION LITHOGRAPHY 审中-公开
标题翻译：间隔辅助切片分割图
公开(公告)号：WO2013101105A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067926
申请日：2011-12-29
申请人： INTEL CORPORATION , SIVAKUMAR, Swaminathan , TAN, Elliot N.
发明人： SIVAKUMAR, Swaminathan , TAN, Elliot N.
IPC分类号： H01L21/027
CPC分类号： H01L21/02587 , H01L21/02658 , H01L21/0337 , H01L21/28 , H01L21/76816 , H01L29/0684 , Y10S438/942
摘要： Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
摘要翻译：公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次于此。这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。

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