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1. 发明申请

WO2006133042A2 METHOD AND APPARATUS TO FABRICATE POLYMER ARRAYS ON PATTERNED WAFERS USING ELECTROCHEMICAL SYNTHESIS 审中-公开
标题翻译：使用电化学合成法制作聚酰胺阵列的方法和装置
公开(公告)号：WO2006133042A2
公开(公告)日：2006-12-14
申请号：PCT/US2006/021650
申请日：2006-06-02
申请人： INTEL CORPORATION , HOLT, Gordon , BARNETT, Brandon , DUBIN, Valery , GSTREIN, Florian
发明人： HOLT, Gordon , BARNETT, Brandon , DUBIN, Valery , GSTREIN, Florian
IPC分类号： B01J19/00
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

2. 发明申请

WO2016048336A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：WO2016048336A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057585
申请日：2014-09-26
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上，以及去除封闭材料的暴露部分。

3. 发明申请

WO2008048222A2 METHOD AND CMOS-BASED DEVICE TO ANALYZE MOLECULES AND NANOMATERIALS BASED ON THE ELECTRICAL READOUT OF SPECIFIC BINDING EVENTS ON FUNCTIONALIZED ELECTRODES 审中-公开
标题翻译：基于功能化电极上的特定结合事件的电学读出分析分子和纳米材料的方法和基于CMOS的装置
公开(公告)号：WO2008048222A2
公开(公告)日：2008-04-24
申请号：PCT/US2006/030397
申请日：2006-08-03
申请人： INTEL CORPORATION , DUBIN, Valery , GSTREIN, Florian , LUEKER, Jonathan
发明人： DUBIN, Valery , GSTREIN, Florian , LUEKER, Jonathan
IPC分类号： G01N33/543
CPC分类号： C12Q1/6816 , C12Q2565/607
摘要： A device having a functionalized electrode having a probe molecule, wherein the device has an ability to electrically detect a molecular binding event between the probe molecule and a target molecule by a polarization change of the functionalized electrode is disclosed. The device could also include an unfunctionalized electrode that does not have the probe molecule and the device could have an ability to electrically detect the molecular binding event between the probe molecule and the target molecule by a polarization change between the functionalized electrode and the unfunctionalized electrode.
摘要翻译：具有带探针分子的功能化电极的装置被公开，其中该装置具有通过功能化电极的极化变化来电检测探针分子和靶分子之间的分子结合事件的能力。该装置还可以包括不具有探针分子的非功能化电极，并且装置可以具有通过功能化电极和未功能化电极之间的极化变化来电检测探针分子和目标分子之间的分子结合事件的能力。

4. 发明申请

WO2006133318A1 CARBON NANOTUBE INTERCONNECT CONTACTS 审中-公开
标题翻译：碳纳米管互连联系
公开(公告)号：WO2006133318A1
公开(公告)日：2006-12-14
申请号：PCT/US2006/022183
申请日：2006-06-06
申请人： INTEL CORPORATION , GSTREIN, Florian , LAVOIE, Adrien , DUBIN, Valery
发明人： GSTREIN, Florian , LAVOIE, Adrien , DUBIN, Valery
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53276 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect on a semiconductor suabstrate comprises providing at least one carbon nanotube (304) within a trench, etching at least one portion of the carbon nanotube to create an opening (602) conformally depositing a metal layer on the carbon nanotube through the opening, and forming a metallized contact (308) at the opening that is substantially coupled to the carbon nanotube. The metal layer may be conformally deposited on the carbon nanotube using an atomic layer depositionm process or an electroless plating process. Multiple metal layers may be deposited to substantially fill voids within the carbon nanotube. The electroless plating process may use as supercritical liquid as the medium for the plating solution. The wetting behavior of the carbon nanotube may be modified prior to the electroless plating process to increase the hydrophilicity of the carbon nanotube.
摘要翻译：一种用于在半导体衬底上形成互连的方法包括在沟槽内提供至少一个碳纳米管（304），蚀刻所述碳纳米管的至少一部分以形成在所述碳纳米管上共形沉积金属层的开口（602），所述开口（602）通过并且在基本上与碳纳米管耦合的开口处形成金属化接触（308）。金属层可以使用原子层沉积工艺或无电镀工艺共形沉积在碳纳米管上。可以沉积多个金属层以基本上填充碳纳米管内的空隙。化学镀处理可以用作超临界液体作为电镀溶液的介质。可以在化学镀处理之前改变碳纳米管的润湿性能，以增加碳纳米管的亲水性。

5. 发明申请

WO2018118092A1 ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES 审中-公开
公开(公告)号：WO2018118092A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068586
申请日：2016-12-23
申请人： INTEL CORPORATION , SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
发明人： SCHENKER, Richard E. , BRISTOL, Robert L. , LIN, Kevin L. , GSTREIN, Florian , BLACKWELL, James M. , KRYSAK, Marie , CHANDHOK, Manish , NYHUS, Paul A. , WALLACE, Charles H. , WARD, Curtis W. , SIVAKUMAR, Swaminathan , TAN, Elliot N.
IPC分类号： H01L21/768 , H01L21/027
摘要： Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

6. 发明申请

WO2018118089A1 DIFFERENTIATED MOLECULAR DOMAINS FOR SELECTIVE HARDMASK FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018118089A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068582
申请日：2016-12-23
申请人： INTEL CORPORATION , HAN, Eungnak , HOURANI, Rami , GSTREIN, Florian , SINGH, Gurpreet , CLENDENNING, Scott B. , LIN, Kevin L. , CHANDHOK, Manish
发明人： HAN, Eungnak , HOURANI, Rami , GSTREIN, Florian , SINGH, Gurpreet , CLENDENNING, Scott B. , LIN, Kevin L. , CHANDHOK, Manish
IPC分类号： H01L21/768 , H01L21/033
摘要： Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

7. 发明申请

WO2016175782A1 MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：微电子导电路线及其制造方法
公开(公告)号：WO2016175782A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028209
申请日：2015-04-29
申请人： INTEL CORPORATION , CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
发明人： CHAWLA, Jasmeet S. , HOURANI, Rami , KOBRINSKY, Mauro J. , GSTREIN, Florian , CLENDENNING, Scott B. , ROBERTS, Jeanette M.
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L2221/1063
摘要： A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
摘要翻译：可以形成包括导电迹线和导电通孔的导电路径结构，其中导电通孔直接接触导电迹线。在一个实施例中，可以通过在导电迹线上形成介电材料层来形成导电路径结构。可以通过介电材料层形成通孔开口以暴露导电迹线的一部分，并且阻挡层可以仅来自导电迹线的暴露部分。可以在通孔开口的侧壁上形成阻挡线，然后可以去除阻挡层。然后可以在通孔开口内形成导电通孔，其中导电通孔直接接触导电迹线。

8. 发明申请

WO2016099570A1 SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：选择性沉积利用半导体器件的极化阻挡层
公开(公告)号：WO2016099570A1
公开(公告)日：2016-06-23
申请号：PCT/US2014/071717
申请日：2014-12-19
申请人： INTEL CORPORATION , KLOSTER, Grant , CLENDENNING, Scott B. , HOURANI, Rami , LIAO, Szuya S. , ROMERO, Patricio E. , GSTREIN, Florian
发明人： KLOSTER, Grant , CLENDENNING, Scott B. , HOURANI, Rami , LIAO, Szuya S. , ROMERO, Patricio E. , GSTREIN, Florian
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/31058 , H01L21/31133 , H01L21/32 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L29/0649 , H01L29/0673 , H01L29/42368 , H01L29/42392 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/786
摘要： Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
摘要翻译：公开了在半导体结构上选择性地沉积高K栅极电介质的方法。该方法包括提供设置在半导体衬底之上的半导体结构。半导体结构设置在隔离侧壁旁边。牺牲阻挡层然后选择性地沉积在隔离侧壁上，而不是半导体结构上。此后，高K栅极电介质沉积在半导体结构上，但不沉积在牺牲阻挡层上。牺牲阻挡层的性质防止氧化物材料在其表面上的沉积。然后进行热处理以去除牺牲阻挡层，从而仅在半导体结构上形成高K栅极电介质。

9. 发明申请

WO2019066825A1 PASSIVATION LAYER FOR GERMANIUM SUBSTRATE 审中-公开
公开(公告)号：WO2019066825A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053843
申请日：2017-09-27
申请人： INTEL CORPORATION , ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
发明人： ROMERO, Patricio E. , CLENDENNING, Scott B. , GSTREIN, Florian , TAN, Cen
IPC分类号： H01L21/02 , H01L29/78
摘要： Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

10. 发明申请

WO2012087547A1 BARRIERLESS SINGLE-PHASE INTERCONNECT 审中-公开
标题翻译：无障碍单相互连
公开(公告)号：WO2012087547A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/063263
申请日：2011-12-05
申请人： INTEL CORPORATION , AKOLKAR, Rohan N. , GSTREIN, Florian , ZIERATH, Daniel J.
发明人： AKOLKAR, Rohan N. , GSTREIN, Florian , ZIERATH, Daniel J.
IPC分类号： H01L21/28 , H01L21/3205
CPC分类号： H01L23/53261 , H01L21/3105 , H01L21/76825 , H01L21/76826 , H01L21/76877 , H01L21/76882 , H01L23/53247 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.
摘要翻译：形成互连结构的方法和包括所述互连结构的集成电路。该方法包括：在导电层上沉积介电层; 在所述电介质层中形成开口以暴露所述导电层; 形成包含熔点在铜的熔点和钨的熔点之间的金属或化合物的无障碍单相互连。形成包括在开口内和介电层的上表面上沉积一层金属或化合物。优选地，无障碍单相互连包括钴或含钴化合物。因此，包括通孔和相关线路的互连结构由单相金属或化合物构成，而不需要在互连和下面的电介质之间使用不同的材料，从而改善电性能和可靠性并进一步简化互连形成过程。

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