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1. 发明申请

WO2013147742A1 METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS 审中-公开
标题翻译：选择性地增加对8T位单元阵列和/或其他逻辑块的操作电压和控制的方法和系统
公开(公告)号：WO2013147742A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/030627
申请日：2012-03-26
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , GEUSKENS, Bibiche M. , TSCHANZ, James , DE, Vivek K. , KHELLAH, Muhammad M.
发明人： KULKARNI, Jaydeep P. , GEUSKENS, Bibiche M. , TSCHANZ, James , DE, Vivek K. , KHELLAH, Muhammad M.
IPC分类号： G11C5/14 , G11C8/10 , G06F13/14
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译：提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。可以在读取模式期间增强单元格Vcc，并且/或者可以用增强来确定写入字线（WWL）和/或读取字线（RWL）。字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平转换器的延迟来延迟保持器控制的逻辑，以减少在初始NAND评估阶段。

2. 发明申请

WO2011163022A2 MEMORY WRITE OPERATION METHODS AND CIRCUITS 审中-公开
标题翻译：存储器写操作方法和电路
公开(公告)号：WO2011163022A2
公开(公告)日：2011-12-29
申请号：PCT/US2011/040458
申请日：2011-06-15
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , KHELLAH, Muhammad M. , GEUSKENS, Bibiche M. , RAYCHOWDHURY, Arijit , KARNIK, Tanay , DE, Vivek, K.
发明人： KULKARNI, Jaydeep P. , KHELLAH, Muhammad M. , GEUSKENS, Bibiche M. , RAYCHOWDHURY, Arijit , KARNIK, Tanay , DE, Vivek, K.
IPC分类号： G11C8/08 , G11C7/10 , G11C7/12
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

3. 发明申请

WO2013100983A1 RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：用于动态变化公差的弹性寄存器文件电路及其操作方法
公开(公告)号：WO2013100983A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067632
申请日：2011-12-28
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , BOWMAN, Keith A. , TSCHANZ, James W. , DE, Vivek K.
发明人： KULKARNI, Jaydeep P. , BOWMAN, Keith A. , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： G11C29/42
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译：所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。

4. 发明申请

WO2013002868A2 CIRCUITS AND METHODS FOR MEMORY 审中-公开
标题翻译：记忆的电路和方法
公开(公告)号：WO2013002868A2
公开(公告)日：2013-01-03
申请号：PCT/US2012/032688
申请日：2012-04-09
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
发明人： KULKARNI, Jaydeep P. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
CPC分类号： G11C7/02 , G11C11/419
摘要： Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
摘要翻译：给出了可以允许较小的最小信元供应（Vmin）而不必增加设备尺寸的数据依赖提升（DDB）位单元的实施例。

5. 发明申请

WO2017091277A1 APPARATUS AND METHOD FOR REDUCING di/dt DURING POWER WAKE-UP 审中-公开
标题翻译：减少功率唤醒期间di / dt的装置和方法
公开(公告)号：WO2017091277A1
公开(公告)日：2017-06-01
申请号：PCT/US2016/050807
申请日：2016-09-08
申请人： INTEL CORPORATION
发明人： SHIM, Yong , KULKARNI, Jaydeep P. , MEINERZHAGEN, Pascal A. , KHELLAH, Muhammad M.
IPC分类号： G06F1/26 , H03K17/041
CPC分类号： H03K17/08104 , H03K3/0377 , H03K17/145 , H03K19/0016
摘要： Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
摘要翻译：描述了一种设备，其包括：耦合到非门控电源节点和门控电源节点的功率门晶体管，功率门晶体管具有门极端; 电阻器件; 与电阻器件串联耦合在一起形成一对的第一晶体管，第一晶体管也耦合到功率门晶体管的栅极端子; 并联耦合到所述第一晶体管和电阻器件的所述串联耦合对的电容器件; 以及耦合到功率门晶体管和非门电源节点的栅极端的第二晶体管。

6. 发明申请

WO2015148074A1 ASSIST CIRCUIT FOR MEMORY 审中-公开
标题翻译：记忆辅助电路
公开(公告)号：WO2015148074A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018518
申请日：2015-03-03
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , THAPLOO, Anupama , RAJWANI, Iqbal , KOO, Kyung-Hoae , KARL, Eric A. , KHELLAH, Muhammad
IPC分类号： G11C7/10 , G11C7/06 , G11C8/08
CPC分类号： G11C7/12 , G11C7/1048 , G11C7/1069 , G11C7/22 , G11C11/419 , G11C17/16 , G11C2207/005
摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
摘要翻译：实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

7. 发明申请

WO2017204956A1 APPARATUS AND METHOD FOR REDUCING di/dt 审中-公开
标题翻译：减少di / dt的装置和方法
公开(公告)号：WO2017204956A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/028637
申请日：2017-04-20
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , SHIM, Yong , MEINERZHAGEN, Pascal A.
IPC分类号： H02M3/07
CPC分类号： G06F1/324 , G06F1/3287 , G06F1/3296 , H02M3/07 , Y02D10/171 , Y02D10/172
摘要： Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
摘要翻译：描述了一种设备，其包括：耦合到非门控电源节点和门控电源节点的可控功率门; 以及电荷泵电路，其可操作用于根据逻辑来导通和关断，其中所述电荷泵电路并联耦合到所述可控功率门并且还耦合到所述非门电源节点和所述门控电源节点。 p>

8. 发明申请

WO2015094374A1 APPARATUS FOR CHARGE RECOVERY DURING LOW POWER MODE 审中-公开
标题翻译：低功耗模式下充电恢复的装置
公开(公告)号：WO2015094374A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/077277
申请日：2013-12-20
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , MEINERZHAGEN, Pascal A. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： H02J7/00
CPC分类号： H02M3/073 , G06F3/041 , H02J7/00 , H03K3/0377 , H03K19/21
摘要： Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
摘要翻译：描述了一种用于电源管理的设备。该装置包括：第一电源节点; 第二电源节点; 耦合到所述第一电源节点和所述第二电源节点的可控设备，所述可控设备可操作以将所述第一电源节点缩短到所述第二电源节点; 耦合到所述第二电源节点的负载; 以及耦合到第一和第二电源节点的电荷恢复泵（CRP）。

9. 发明申请

WO2014004011A1 APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY 审中-公开
标题翻译：用于减少存储器的最小供电电压的装置
公开(公告)号：WO2014004011A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/044362
申请日：2013-06-05
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , KHELLAH, Muhammad M. , TSCHANZ, James W. , GEUSKENS, Bibiche M. , DE, Vivek K.
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C11/419 , G11C7/227 , G11C11/412 , G11C11/413
摘要： Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.
摘要翻译：描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到所述第一供应节点和第二供应节点的功率设备，所述第二供应节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平操作。

10. 发明申请

WO2017160414A1 REDUCED SWING BIT-LINE APPARATUS AND METHOD 审中-公开
标题翻译：减少摆动双线设备和方法
公开(公告)号：WO2017160414A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/016050
申请日：2017-02-01
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , RAJWANI, Iqbal R. , DONKOH, Eric
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18
CPC分类号： G11C11/419
摘要： Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower V MIN , higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.
摘要翻译：描述了一种装置，其包括：位线（BL）读取端口; 耦合到BL读取端口的第一本地位线（LBL）第二个LBL; 以及耦合到第一和第二LBL的一个或多个削波器设备。该装置允许将低摆动位线用于大信号存储器阵列。低摆动操作可减少开关动态电容。该装置还描述了用于位线保持器控制的分离输入NAND / NOR门，其实现了较低的V MIN，较高的噪声容限以及改进的保持器老化缓解。还描述了一种用于低摆动写入操作的装置，其可以在高电压下启用而不降低低电压操作。

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