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1. 发明申请

WO2018236377A1 UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS 审中-公开
公开(公告)号：WO2018236377A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038681
申请日：2017-06-22
申请人： INTEL CORPORATION
发明人： GUO, Zheng , ONG, Clifford L. , KARL, Eric A. , BOHR, Mark T.
IPC分类号： H01L27/11 , H01L27/06
摘要： Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

2. 发明申请

WO2015148074A1 ASSIST CIRCUIT FOR MEMORY 审中-公开
标题翻译：记忆辅助电路
公开(公告)号：WO2015148074A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/018518
申请日：2015-03-03
申请人： INTEL CORPORATION
发明人： KULKARNI, Jaydeep P. , THAPLOO, Anupama , RAJWANI, Iqbal , KOO, Kyung-Hoae , KARL, Eric A. , KHELLAH, Muhammad
IPC分类号： G11C7/10 , G11C7/06 , G11C8/08
CPC分类号： G11C7/12 , G11C7/1048 , G11C7/1069 , G11C7/22 , G11C11/419 , G11C17/16 , G11C2207/005
摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
摘要翻译：实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

3. 发明申请

WO2013101250A1 OPERATION AWARE AUTO-FEEDBACK SRAM 审中-公开
标题翻译：操作注意自动反馈SRAM
公开(公告)号：WO2013101250A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068286
申请日：2011-12-31
申请人： INTEL CORPORATION , KOLAR, Pramod , KARL, Eric A.
发明人： KOLAR, Pramod , KARL, Eric A.
IPC分类号： G11C11/413 , G11C5/14
CPC分类号： G11C11/412 , G11C11/419
摘要： A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.
摘要翻译：描述了静态随机存取存储器。 SRAM包括存储单元和电压源，以在写入操作期间向存储单元提供降低的电压。 SRAM单元包括第一通道门和第二通道门。第一电阻器耦合在第一通道栅极和存储单元的第一侧之间。第二电阻器耦合在第二通道栅极和存储单元的第二侧之间。

4. 发明申请

WO2020257067A1 MULTI-BIT READ-ONLY MEMORY DEVICE 审中-公开
公开(公告)号：WO2020257067A1
公开(公告)日：2020-12-24
申请号：PCT/US2020/037326
申请日：2020-06-11
申请人： INTEL CORPORATION
发明人： WANG, Xiaofei , SOMASEKHAR, Dinesh , ONG, Clifford , KARL, Eric A. , GUO, Zheng , CARSKADON, Gordon
IPC分类号： G11C11/56 , G11C16/08 , G11C16/26
摘要： Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

5. 发明申请

WO2015134013A1 APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY 审中-公开
标题翻译：适用于记忆的自适应写入辅助装置
公开(公告)号：WO2015134013A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/020828
申请日：2014-03-05
申请人： INTEL CORPORATION
发明人： SHAMANNA, Gururaj K. , RUSU, Stefan , KARL, Eric A. , GUO, Zheng
IPC分类号： G11C7/22 , G11C11/419
CPC分类号： G11C11/419 , G11C7/04 , G11C7/22 , G11C29/021 , G11C29/028
摘要： Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.
摘要翻译：描述了一种装置，包括：存储器; 第一电源节点，用于接收第一电源; 耦合到所述存储器以向所述存储器提供第二电源的第二电源节点; 耦合到所述第一和第二电源节点的电路，所述电路可操作以通过自适应地调整写入辅助脉冲的信号特性来动态地调制所述第二电源中的下降。

6. 发明申请

WO2019005135A1 USAGE OF TRENCH CONTACT IN READ ONLY MEMORY PROGRAMMING 审中-公开
公开(公告)号：WO2019005135A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/040429
申请日：2017-06-30
申请人： INTEL CORPORATION , LARYEA, John A. , KANEVSKY, Dmitri Dimak , LI, Kenny K. , KARL, Eric A. , WANG, Xiaofei
发明人： LARYEA, John A. , KANEVSKY, Dmitri Dimak , LI, Kenny K. , KARL, Eric A. , WANG, Xiaofei
IPC分类号： H01L27/112 , H01L21/768
摘要： A memory array and method of forming a memory array including a plurality of transistors arranged in rows on a substrate; a plurality of power lines arranged in rows with respective ones of the plurality of power lines disposed across each of the rows of the plurality of transistors; a plurality of trench contacts disposed in a direction generally orthogonal to the rows of the plurality of transistors, wherein at least one of the plurality of trench contacts includes a length dimension that extends over two adjacent rows of the plurality of transistors, wherein the at least one of the plurality of trench contacts is coupled to a diffusion region of each of the adjacent rows of the plurality of transistors; and a power via contact between the at least one of the plurality of trench contacts and one of the plurality of power lines.

7. 发明申请

WO2018236362A1 INTERNAL NODE JUMPER FOR MEMORY BIT CELLS 审中-公开
公开(公告)号：WO2018236362A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038389
申请日：2017-06-20
申请人： INTEL CORPORATION , SHRIDHARAN, Smita , GUO, Zheng , KARL, Eric A. , SHCHUPAK, George , KOSINOVSKY, Tali
发明人： SHRIDHARAN, Smita , GUO, Zheng , KARL, Eric A. , SHCHUPAK, George , KOSINOVSKY, Tali
IPC分类号： H01L27/06 , H01L29/06 , H01L27/11
摘要： Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

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