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1. 发明申请

WO2017123327A1 TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MULTIPLE DATA CHANNELS 审中-公开
标题翻译：通过多个数据通道访问或操作双列内存模块的技术
公开(公告)号：WO2017123327A1
公开(公告)日：2017-07-20
申请号：PCT/US2016/063106
申请日：2016-11-21
申请人： INTEL CORPORATION
发明人： COX, Christopher E. , BAINS, Kuljit S. , VERGIS, George , NALE, Bill , MCCALL, James A. , ZHAO, Chong J. , SAH, Suneeta , VOGT, Pete D. , GOLES, John R.
IPC分类号： G06F13/16
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/04 , G11C7/10 , G11C7/1045 , G11C11/4096 , G11C14/0009
摘要： Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
摘要翻译：示例包括通过一个或多个数据通道访问或操作双列直插式内存模块（DIMM）的技术。在一些示例中，DIMM处或其上的存储器设备可以经由一个或多个数据通道来访问。所述一个或多个数据通道被布置成使得DIMM被配置为以包括两个数据通道的双通道模式操作或者以包括单个数据通道的单通道模式操作。

2. 发明申请

WO2018064424A1 EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET AND CONFIGURED FOR INCREASED PERFORMANCE 审中-公开
标题翻译：扩展平台，每个CPU插槽有额外的内存模块插槽，配置提高性能
公开(公告)号：WO2018064424A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/054190
申请日：2017-09-28
申请人： INTEL CORPORATION
发明人： QUERBACH, Bruce , VOGT, Pete D.
IPC分类号： G11C5/04 , G06F1/18
摘要： Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive at least one memory module, the second row of elements positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.
摘要翻译：描述了包括配置为接受CPU和存储器模块的印刷电路板的电子设备和方法。一种装置包括印刷电路板（PCB），该印刷电路板包括限定长度和宽度的印刷电路板，该长度大于宽度。该装置包括PCB上的第一行元件，包括配置为接收至少一个存储器模块的第一存储器区域。该装置包括在PCB上的第二行元件，包括被配置为容纳第一CPU的第一中央处理单元（CPU）插槽以及被配置为容纳第二CPU的第二CPU插槽，第一CPU插槽和第二CPU插槽沿着PCB的宽度并排放置。该装置还包括在PCB上的第三行元件，包括配置为接收至少一个存储器模块的第二存储器区域，第二行元件位于第一行元件和第三行元件之间。描述并要求保护其他实施例。

3. 发明申请

WO2014046751A1 METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY 审中-公开
标题翻译：用于评估输入/输出缓冲器电路的方法，系统和装置
公开(公告)号：WO2014046751A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/045796
申请日：2013-06-14
申请人： INTEL CORPORATION
发明人： NELSON, Christopher J. , MAK, Tak M. , ZIMMERMAN, David J. , VOGT, Pete D.
IPC分类号： G01R29/02 , G01R31/317 , G11C7/10
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
摘要翻译：用于评估I / O缓冲电路的技术和机制。在一个实施例中，对包括I / O缓冲器电路的设备执行测试轮，每个测试轮包括对于每个I / O缓冲器电路的相应回环测试。每个测试轮对应于发射时钟信号和接收时钟信号之间的不同的相应延迟。在另一个实施例中，第一测试轮指示至少一个I / O缓冲器电路的故障条件，第二测试轮指示每个I / O缓冲电路的故障条件。 I / O缓冲电路的评估确定装置是否满足测试条件，其中确定是基于与第一测试轮对应的延迟与对应于第二测试轮的延迟之间的差。

4. 发明申请

WO2018064421A1 EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET 审中-公开
标题翻译：每个CPU插槽带有额外的内存模块插槽的扩展平台
公开(公告)号：WO2018064421A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/054186
申请日：2017-09-28
申请人： INTEL CORPORATION
发明人： QUERBACH, Bruce , VOGT, Pete D.
IPC分类号： G11C5/04 , G06F1/18
CPC分类号： G11C5/06 , G06F1/18 , G11C5/04 , G11C5/063 , G11C5/066 , H01R12/716 , H05K1/0295 , H05K1/141 , H05K1/181 , H05K2201/09409 , H05K2201/10159
摘要： Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.
摘要翻译：描述了包括配置为接受CPU和存储器模块的印刷电路板的电子设备和方法。一种设备包括印刷电路板，印刷电路板包括第一行元件，第一行元件包括位于第一和第二组双列直插式存储器模块（DIMM）之间的第一CPU。印刷电路板还包括第二行元件，包括位于第三和第四组DIMM之间的第二CPU。该设备还包括包括第五组DIMM的第三行元件，其中第二行元件位于第一行元件和第三行元件之间。描述并要求保护其他实施例。

5. 发明申请

WO2014209936A1 EMBEDDED ECC ADDRESS MAPPING 审中-公开
标题翻译：嵌入式ECC地址映射
公开(公告)号：WO2014209936A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/043766
申请日：2014-06-24
申请人： INTEL CORPORATION , VOGT, Pete D.
发明人： VOGT, Pete D.
IPC分类号： G01F11/10 , G06F12/02
CPC分类号： G06F11/1052
摘要： Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive a request to read or write data to a memory device, wherein the data is mapped to a memory page comprising a plurality of cache lines, displace at least a portion of the plurality of cache lines to embed error correction code information with the data, and remap the portion of the plurality of cache lines to another memory location, and retrieve or store the data and the error correction code information on the memory page. Other embodiments are also disclosed and claimed.
摘要翻译：描述了将ECC数据与高速缓存线数据嵌入存储器页面的装置，系统和方法。在一个实施例中，电子设备包括处理器和存储器控制逻辑，用于接收将数据读取或写入存储器设备的请求，其中数据被映射到包括多个高速缓存行的存储器页面，将至少一部分以将所述数据的纠错码信息嵌入到所述多个高速缓存行中，并且将所述多个高速缓存行的所述部分重新映射到另一个存储器位置，并且将所述数据和所述纠错码信息检索或存储在所述存储器页面上。还公开并要求保护其他实施例。

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