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1. 发明申请

WO2017105708A1 SORTING DATA AND MERGING SORTED DATA IN AN INSTRUCTION SET ARCHITECTURE 审中-公开
标题翻译：在指令集体系结构中排序数据并合并分类数据
公开(公告)号：WO2017105708A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/061901
申请日：2016-11-14
申请人： INTEL CORPORATION
发明人： MISHRA, Asit K. , MARR, Deborah T. , PARK, Jong Soo , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , ANDERSON, Michael , PATWARY, Mostofa Ali , SUNDARAM, Narayanan , LI, Sheng
IPC分类号： G06F9/38
CPC分类号： G06F9/30192 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145
摘要： A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.
摘要翻译：处理装置包括分类模块，其将多个元素中的每一个添加到寄存器静止中的对应位置的位置值，从而导致在相应位置中的多个变换元素。多个元素包括多个比特。排序模块将多个变换元素中的每一个与自身和彼此进行比较。排序模块还基于比较将多个变换元素中的每一个分配启用或禁用指示符中的一个。排序模块还对分配给多个变换元素中的每一个的启用指示符的数量进行计数，以生成多个元素的排序序列。

2. 发明申请

WO2019066832A1 MAGNETIC CORE INDUCTORS 审中-公开
公开(公告)号：WO2019066832A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053859
申请日：2017-09-28
申请人： INTEL CORPORATION
发明人： ZHAO, Junnan , WANG, Ying , XU, Cheng , LEE, Kyu Oh , LI, Sheng , DENG, Yikang
IPC分类号： H01F27/00 , H01F41/00
摘要： Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

3. 发明申请

WO2016130282A1 PERFORMING POWER MANAGEMENT IN A MULTICORE PROCESSOR 审中-公开
标题翻译：在多处理器中执行电源管理
公开(公告)号：WO2016130282A1
公开(公告)日：2016-08-18
申请号：PCT/US2016/013869
申请日：2016-01-19
申请人： INTEL CORPORATION
发明人： LEE, Victor W. , KIM, Daehyun , BAI, Yuxin , JI, Shihao , LI, Sheng , KALAMKAR, Dhiraj D. , MELLEMPUDI, Naveen K.
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/3296 , G06F9/5088 , G06F9/5094 , Y02D10/124 , Y02D10/126 , Y02D10/172 , Y02D10/22 , Y02D10/32
摘要： In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器用于独立地执行指令的多个核心，所述核心包括存储性能信息的多个计数器，以及耦合到所述多个核心的功率控制器，所述功率控制器具有从其中接收性能信息的逻辑至少部分地基于性能信息和模型信息来确定多个计数器中的一些，以确定要激活的核心数量和用于下一个操作间隔的核心数量的性能状态，并且引起核心数量在下一操作间隔期间处于活动状态，所述性能信息与所述多个核心中的一个或多个核心上的工作负载的执行相关联。描述和要求保护其他实施例。

4. 发明申请

WO2018182613A1 FORMATION OF TALL METAL PILLARS USING MULTIPLE PHOTORESIST LAYERS 审中-公开
公开(公告)号：WO2018182613A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024999
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： CHAVALI, Sri Chaitra J. , CHENG, Liwei , ALUR, Siddharth K. , LI, Sheng
IPC分类号： H01L21/768
摘要： An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.

5. 发明申请

WO2017160459A1 PLASMA ETCHING OF SOLDER RESIST OPENINGS 审中-公开
标题翻译：等离子刻蚀抗焊剂开口
公开(公告)号：WO2017160459A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018195
申请日：2017-02-16
申请人： INTEL CORPORATION
发明人： DARMAWIKARTA, Kristof , JAIN, Rahul , MAY, Robert Alan , LI, Sheng , BOYAPATI, Sri Ranga Sai
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/3213 , H01L21/225
CPC分类号： H05K3/0041 , H05K1/0313 , H05K1/09 , H05K3/0055 , H05K3/3452 , H05K2203/0502 , H05K2203/0548 , H05K2203/0562 , H05K2203/0588 , H05K2203/095
摘要： A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.
摘要翻译：
一种形成电子组件的方法。该方法包括用阻焊剂覆盖介电层上的图案化导电层; 在所述阻焊剂上沉积金属层; 在所述金属层上沉积光刻胶; 构图光刻胶; 蚀刻从光致抗蚀剂暴露的金属层以形成金属掩模; 去除光刻胶; 并等离子蚀刻从金属掩模暴露的阻焊层。用于电子卡安全保护的电子组件。该电子组件包括位于电介质层上的图案化导电层; 以及覆盖图案化导电层和介电层的阻焊剂，其中阻焊剂包括暴露图案化导电层的开口，其中阻焊剂中的开口仅在各个开口的侧壁上具有有机材料。

6. 发明申请

WO2016130311A1 PERFORMING POWER MANAGEMENT IN A MULTICORE PROCESSOR 审中-公开
标题翻译：在多处理器中执行电源管理
公开(公告)号：WO2016130311A1
公开(公告)日：2016-08-18
申请号：PCT/US2016/014830
申请日：2016-01-26
申请人： INTEL CORPORATION
发明人： LEE, Victor W. , GROCHOWSKI, Edward T. , KIM, Daehyun , BAI, Yuxin , LI, Sheng , MELLEMPUDI, Naveen K. , KALAMKAR, Dhiraj D.
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3287 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/329 , G06F1/3296 , G06F9/50 , Y02D10/126 , Y02D10/14 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个第一核，用于独立地执行指令，所述多个第一核中的每一个包括存储执行信息的多个计数器; 用于执行存储器操作的至少一个第二核心; 以及功率控制器，用于从所述多个计数器中的至少一些计数器接收性能信息，至少部分地基于所述性能信息确定在所述处理器上执行的工作负载类型，并且基于所述工作负载类型，动态地从一个或多个计算机迁移一个或多个线程或多个第一核心到至少一个第二核心，以在下一个操作间隔期间执行。描述和要求保护其他实施例。

7. 发明申请

WO2020005423A1 EMBEDDED MAGNETIC INDUCTOR 审中-公开
公开(公告)号：WO2020005423A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/033538
申请日：2019-05-22
申请人： INTEL CORPORATION
发明人： BROWN, Andrew J. , JAIN, Rahul , LI, Sheng , VADLAMANI, Sai , ZHANG, Chong
IPC分类号： H01F17/00 , H01F5/00 , H01F27/28
摘要： An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.

8. 发明申请

WO2018182597A1 MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER 审中-公开
公开(公告)号：WO2018182597A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/024795
申请日：2017-03-29
申请人： INTEL CORPORATION , MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
发明人： MAY, Robert Alan , SALAMA, Islam A. , BOYAPATI, Sri Ranga Sai , LI, Sheng , DARMAWIKARTA, Kristof , SANKMAN, Robert L. , ALUR, Amruthavalli Pallavi
IPC分类号： H01L25/065 , H01L23/00 , H01L25/07
摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

9. 发明申请

WO2018004822A1 HIGH RESOLUTION SOLDER RESIST MATERIAL FOR SILICON BRIDGE APPLICATION 审中-公开
标题翻译：用于硅桥应用的高分辨率焊料电阻材料
公开(公告)号：WO2018004822A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/030888
申请日：2017-05-03
申请人： INTEL CORPORATION
发明人： ALUR, Siddharth K. , LI, Sheng , JEN, Wei-Lun K.
IPC分类号： H01L23/482 , H01L23/48 , H01L23/00
摘要： In accordance with disclosed embodiments, there are provided high resolution solder resist material for silicon bridge application. For instance, in accordance with one embodiment, there is a silicon bridge disclosed, the silicon bridge having therein a solder resist layer formed from a high resolution solder resist material; in which the solder resist layer includes a polymer material which hardens when exposed to light radiation; in which the solder resist layer further includes spherical particles; a plurality of vias patterned into the solder resist layer by a photolithography process, the plurality of vias forming a set of larger vias and a set of smaller vias patterned into the solder resist layer by the photolithography process, each of the larger vias being greater in size than each of the smaller vias, and further in which each of the smaller vias are less than half the size of any one of the larger vias; in which the larger vias and the smaller vias provide through-silicon vias (TSVs) interconnects through the solder resist layer electrically interfacing two or more functional semiconductor devices affixed to the silicon bridge; and the silicon bridge further having therein a copper layer positioned below the solder resist layer. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于硅桥应用的高分辨率阻焊剂材料。例如，根据一个实施例，公开了一种硅桥，所述硅桥中具有由高分辨率阻焊材料形成的阻焊层; 其中阻焊层包括暴露于光辐射时硬化的聚合物材料; 其中阻焊层还包括球形颗粒; 通过光刻工艺图案化到阻焊层中的多个通孔，多个通孔形成一组较大的通孔和一组通过光刻工艺图案化到阻焊层中的较小的通孔，每个较大的通孔在尺寸小于每个较小的通孔，并且进一步其中每个较小的通孔小于任何一个较大的通孔的尺寸的一半; 其中较大的通孔和较小的通孔提供贯穿硅通孔（TSV）互连穿过阻焊层，所述阻焊层电连接固定到硅桥的两个或更多个功能半导体器件; 并且硅桥还具有位于阻焊层下方的铜层。披露了其他相关的实施例。

10. 发明申请

WO2017112182A1 APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS 审中-公开
标题翻译：用于加速图解分析的装置和方法
公开(公告)号：WO2017112182A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062784
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： ANDERSON, Michael , LI, Sheng , PARK, Jong Soo , PATWARY, Md Mostofa Ali , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , SUNDARAM, Narayanan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30192 , G06F9/3802 , G06F12/0811 , G06F12/084 , G06F2212/455
摘要： An apparatus and method are described for accelerating graph analytics. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch program code including set intersection and set union operations; a graph accelerator unit (GAU) to execute at least a first portion of the program code related to the set intersection and set union operations and generate results; and an execution unit to execute at least a second portion of the program code using the results provided from the GAU.
摘要翻译：描述了用于加速图分析的装置和方法。例如，处理器的一个实施例包括：指令获取单元，用于获取包括集合交集和设置联合操作的程序代码; 图形加速器单元（GAU），用于执行与所述集合交集有关的程序代码的至少第一部分并设置联合操作并生成结果; 以及执行单元，用于使用从GAU提供的结果来执行程序代码的至少第二部分。

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