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1. 发明申请

WO2016014212A1 SELECTIVE CONTROL OF ON-DIE TERMINATION IN A MULTI-RANK SYSTEM 审中-公开
标题翻译：多级系统中的终端终止的选择性控制
公开(公告)号：WO2016014212A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/038003
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit , BONEN, Nadav
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： H03K19/0005 , G06F3/0604 , G06F3/061 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/4086 , H03K19/0008 , H03K19/017545 , H03K19/01825 , H03K19/018557
摘要： A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
摘要翻译：存储器子系统包括多器件封装，其包括被组织为多级存储器的多个存储器件。用于存储器子系统的控制单元向存储器的一些或全部行同时发送存储器访问命令，并且触发接收存储器访问命令的所有存储器等级的一部分以改变管芯终端（ODT）设置。选择其中一个行执行存储器访问命令，并且在所有等级触发以改变ODT设置的情况下执行命令具有改变的ODT设置。

2. 发明申请

WO2020005457A1 ARCHITECTURE FOR DYNAMIC TRANSFORMATION OF MEMORY CONFIGURATION 审中-公开
公开(公告)号：WO2020005457A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/034737
申请日：2019-05-30
申请人： INTEL CORPORATION
发明人： BONEN, Nadav , MANDELBLAT, Julius , SUCHER, Nir
IPC分类号： G06F3/06 , G06F13/40 , G06F13/16
摘要： One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

3. 发明申请

WO2016048634A1 EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM 审中-公开
标题翻译：存储器和主机系统之间交换ECC元数据
公开(公告)号：WO2016048634A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/048776
申请日：2015-09-08
申请人： INTEL CORPORATION
发明人： BONEN, Nadav , BAINS, Kuljit , HALBERT, John
IPC分类号： G06F11/10 , G06F12/00 , G06F13/16
CPC分类号： G06F11/1076 , G06F11/1004 , G06F11/1048
摘要： Exposing internal error correction bits from a memory device for use as metadata bits by an external memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device exposes the internal error correction bits to the memory controller to allow the memory controller to use the data.
摘要翻译：从存储器件中公开内部纠错位，用于由外部存储器控制器用作元数据位。在第一模式中，存储器件在存储器件处应用用于内部纠错的内部纠错位。在第二模式中，存储器件将内部纠错位公开到存储器控制器以允许存储器控制器使用数据。

4. 发明申请

WO2017160527A1 ASYMMETRICAL MEMORY MANAGEMENT 审中-公开
标题翻译：非对称存储器管理
公开(公告)号：WO2017160527A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/021040
申请日：2017-03-07
申请人： INTEL CORPORATION
发明人： BONEN, Nadav , GREENFIELD, Zvika , OSBORNE, Randy
IPC分类号： G06F13/16 , G06F12/0802
摘要： Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first and second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.
摘要翻译：这里描述的是用于启用高带宽访问的非对称存储器管理的实施例。在实施例中，可以使用多于一个存储器源的带宽能力来合成高带宽高速缓存或高带宽区域。在一个实施例中，存储器管理电路包括与第一和第二存储器耦合的输入/输出（I / O）电路。 I / O电路将接收内存访问请求。存储器管理电路包括用于确定存储器访问请求是针对系统存储器的第一区域中的数据还是针对系统存储器的第二区域中的数据以及响应于确定存储器访问请求中的一个是针对第一区域以及第二个存储器访问请求是到第二个区域，从第一个存储器的高速缓存存取第一个区域中的数据，并同时从第二个存储器存取第二个区域中的数据。

5. 发明申请

WO2016160137A1 ASYMMETRIC SET COMBINED CACHE 审中-公开
标题翻译：不对称设置组合缓存
公开(公告)号：WO2016160137A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/017340
申请日：2016-02-10
申请人： INTEL CORPORATION
发明人： GREENFIELD, Zvika , BONEN, Nadav , DIAMAND, Israel
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0808 , G06F12/0842 , G06F12/0864 , G06F2212/1016 , G06F2212/62
摘要： Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may include one or more processing cores for processing of data, and a cache memory to cache data from a main memory for the one or more processing cores, the cache memory including a first cache portion, the first cache portion including a direct-mapped cache, and a second cache portion, the second cache portion including a multi-way cache. The cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion. A coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion.
摘要翻译：实施例通常涉及包括直接映射高速缓存部分和多路高速缓存部分的非对称集合组合高速缓存。处理器可以包括用于处理数据的一个或多个处理核心，以及高速缓存存储器，用于从一个或多个处理核心的主存储器缓存数据，所述高速缓冲存储器包括第一高速缓存部分，所述第一高速缓存部分包括直接 - 映射高速缓存和第二高速缓存部分，所述第二高速缓存部分包括多路高速缓存。高速缓冲存储器包括第一高速缓存部分和第二高速缓存部分中的非对称集合，第一高速缓存部分大于第二高速缓存部分。缓存存储器的协调替换策略提供了第一高速缓存部分和第二高速缓存部分中的数据的替换。

6. 发明申请

WO2017052853A1 PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM 审中-公开
标题翻译：多排序系统中可编程的终端定时时序
公开(公告)号：WO2017052853A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/047511
申请日：2016-08-18
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit , KOSTINSKY, Alexey , BONEN, Nadav
IPC分类号： G11C7/10
CPC分类号： H03K19/017545 , G06F3/061 , G06F3/0629 , G06F3/0673 , G06F13/1668
摘要： On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
摘要翻译：片上终端（ODT）控制启用可编程的ODT延迟设置。存储器设备可以通过由多个存储器设备组织的存储器级共享的一个或多个总线耦合到相关联的存储器控制器。存储器控制器产生用于目标等级的存储器访问命令。响应于该命令，存储器件可以基于目标等级或非目标等级，并且基于访问命令是包括读取还是写入，选择性地接合ODT用于存储器访问操作。存储器件可以根据可编程的ODT延迟设置接合ODT。可编程ODT延迟设置可以为读写事务设置不同的ODT时序值。

7. 发明申请

WO2016137760A1 PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP ARCHITECTURE 审中-公开
标题翻译：在银行集团架构的存储设备中预先存储和刷新银行
公开(公告)号：WO2016137760A1
公开(公告)日：2016-09-01
申请号：PCT/US2016/017688
申请日：2016-02-12
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit S. , HALBERT, John B. , BONEN, Nadav , LEVY, Tomer
IPC分类号： G11C11/406 , G11C11/4093 , G11C8/12
CPC分类号： G11C11/40618 , G11C11/40603 , G11C11/40611 , G11C11/4087
摘要： Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.
摘要翻译：内存子系统刷新管理使命令能够使用单个命令来访问不同银行组之间的一个或多个识别的银行。每个银行组分别单独发送在单独的银行组中发送标识银行或银行的命令，该命令可以导致存储设备访问不同银行组中的银行。该命令可以是刷新命令。该命令可以是预充电命令。

8. 发明申请

WO2016105806A1 POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY 审中-公开
标题翻译：基于极值的数据传输功能，用于易失性存储器
公开(公告)号：WO2016105806A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062350
申请日：2015-11-24
申请人： INTEL CORPORATION
发明人： BONEN, Nadav
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F12/0638 , G06F12/0238 , G06F12/0246 , G06F2212/1028 , G06F2212/205 , G06F2212/7201 , G11C7/1006 , G11C7/1072 , G11C11/40615 , G11C14/0045 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus, systems, and methods to implement polarity based data transfer function for volatile memory power reduction are described. The transfer function take into account certain data values, all zeroes in particular, that are common and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values.
摘要翻译：描述了实现用于易失性存储器功率降低的基于极性的数据传递功能的装置，系统和方法。传递函数考虑了特定数据值，特别是所有零值，它们是常见的，并将其转换为消耗较少功率并且较不常见的预定值。类似地，这些预定值被转换为公共值。

9. 发明申请

WO2016048618A1 COMMON DIE IMPLEMENTATION FOR LOW POWER MEMORY DEVICES 审中-公开
标题翻译：低功耗存储器件的通用实现
公开(公告)号：WO2016048618A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/048299
申请日：2015-09-03
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit , BONEN, Nadav , COX, Christopher , MCCALL, James
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/287 , G06F13/1678
摘要： A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus.
摘要翻译：存储器设备和存储器控制器可以通过比存储器件内部的数据总线窄的带宽的系统数据总线进行接口。存储器设备和存储器控制器在突发长度的所有传输周期上通过系统数据总线传送数据，但是发送比用于传送所有可以读取或写入内部数据总线上的所有位的位少的位存储设备。存储器设备可以具有不同的操作模式，以允许基于与较窄带宽系统数据总线接口的能力在不同系统配置中使用公共存储器设备。

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