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1. 发明申请

WO2012177313A2 SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 审中-公开
标题翻译：具有用于嵌入式动态随机存取存储器（EDRAM）的集成四元组电容器的半导体结构及其形成方法
公开(公告)号：WO2012177313A2
公开(公告)日：2012-12-27
申请号：PCT/US2012032064
申请日：2012-04-04
申请人： INTEL CORP , DOYLE BRIAN S , SHAH UDAY , SURI SATYARTH , CHEBIAM RAMANAN V
发明人： DOYLE BRIAN S , SHAH UDAY , SURI SATYARTH , CHEBIAM RAMANAN V
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/10894 , H01L28/91
摘要： Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.
摘要翻译：描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。沟槽有一个底部和侧壁。金属板的四重布置设置在沟槽的底部，与侧壁间隔开。第二电介质层设置在沟槽的侧壁和金属板的四重布置上。顶部金属板层设置在第二介电层上并与第二介质层保形。

2. 发明申请

WO2009032576A3 METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS 审中-公开
标题翻译：制造不同高度的相邻硅片的方法
公开(公告)号：WO2009032576A3
公开(公告)日：2009-05-07
申请号：PCT/US2008074161
申请日：2008-08-25
申请人： INTEL CORP , DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
发明人： DOYLE BRIAN S , JIN BEEN-YIH , SHAH UDAY
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L29/785 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795
摘要： A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin.
摘要翻译：制造具有不同高度的相邻硅鳍的方法包括：提供其上沉积有隔离层的硅衬底;图案化隔离层以形成第一和第二隔离结构;图案化硅衬底以在第一隔离结构下形成第一硅鳍;以及在所述第二隔离结构下方的第二硅鳍状物，在所述衬底上沉积绝缘层，平坦化所述绝缘层以暴露所述第一和第二隔离结构的顶表面，沉积并图案化掩模层以掩蔽所述第一隔离结构而不是所述第二施加湿蚀刻以去除第二隔离结构并暴露第二硅鳍;在第二硅鳍上外延沉积硅层;以及使绝缘层凹陷以暴露第一硅鳍的至少一部分，并且至少第二硅鳍的一部分。

3. 发明申请

WO2007005697A2 BLOCK CONTACT ARCHITECTURES FOR NANOSCALE CHANNEL TRANSISTORS 审中-公开
标题翻译：用于纳米通道晶体管的分块接触结构
公开(公告)号：WO2007005697A2
公开(公告)日：2007-01-11
申请号：PCT/US2006025751
申请日：2006-06-29
申请人： INTEL CORP , RADOSAVLJEVIC MARKO , MAJUMDAR AMLAN , DOYLE BRIAN S , KAVALIEROS JACK , DOCZY MARK L , BRASK JUSTIN K , SHAH UDAY , DATTA SUMAN , CHAU ROBERT S
发明人： RADOSAVLJEVIC MARKO , MAJUMDAR AMLAN , DOYLE BRIAN S , KAVALIEROS JACK , DOCZY MARK L , BRASK JUSTIN K , SHAH UDAY , DATTA SUMAN , CHAU ROBERT S
IPC分类号： H01L29/786 , H01L21/336 , H01L29/417
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78681 , H01L29/78684 , H01L2029/7858
摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
摘要翻译：一种用于纳米级沟道器件的接触结构，其具有接触结构，所述接触结构耦合到具有多个平行半导体本体的器件的源极或漏极区域之间并在所述源极或漏极区域之间延伸。接触结构能够接触具有亚光刻间距的平行半导体本体。

4. 发明申请

WO2015147801A1 TECHNIQUES FOR FORMING NON-PLANAR RESISTIVE MEMORY CELLS 审中-公开
标题翻译：形成非平面电阻记忆细胞的技术
公开(公告)号：WO2015147801A1
公开(公告)日：2015-10-01
申请号：PCT/US2014031735
申请日：2014-03-25
申请人： INTEL CORPORATON , MAJHI PRASHANT , KARPOV ELIJAH V , SHAH UDAY , MUKHERJEE NILOY , KUO CHARLES C , PILLARISETTY RAVI , DOYLE BRIAN S , CHAU ROBERT S
发明人： MAJHI PRASHANT , KARPOV ELIJAH V , SHAH UDAY , MUKHERJEE NILOY , KUO CHARLES C , PILLARISETTY RAVI , DOYLE BRIAN S , CHAU ROBERT S
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2436 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.
摘要翻译：公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。该技术可用于相对于给定存储器单元空间的平面电阻存储器单元来减少所涉及的形成电压要求和/或电阻（例如在低电阻状态期间的电阻）。非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。第二电极可以基本上在开关层的相对部分之间，并且在形成非平面电阻式存储单元之后，第一电极可以基本上与开关层的至少两侧相邻。在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

5. 发明申请

WO2006020158A3 PLANARIZING A SEMICONDUCTOR STRUCTURE TO FORM REPLACEMENT METAL GATES 审中-公开
标题翻译：平面化半导体结构以形成替换金属门
公开(公告)号：WO2006020158A3
公开(公告)日：2006-10-12
申请号：PCT/US2005025339
申请日：2005-07-14
申请人： INTEL CORP , KAVALIEROS JACK , BRASK JUSTIN , DOCZY MARK , SHAH UDAY , BARNS CHRIS , METZ MATTHEW , DATTA SUMAN , CHAU ROBERT
发明人： KAVALIEROS JACK , BRASK JUSTIN , DOCZY MARK , SHAH UDAY , BARNS CHRIS , METZ MATTHEW , DATTA SUMAN , CHAU ROBERT
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/49
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/31111 , H01L21/32134 , H01L21/823807 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.
摘要翻译：包括氮化物和填充层的牺牲栅极结构可以用金属栅极电极代替。金属栅电极可以再次被覆盖有填充层的氮化物层覆盖。氮化物层和填充层的替换可以重新引入应变并提供蚀刻停止。

6. 发明申请

WO2007038575A3 PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY 审中-公开
标题翻译：在大容量基板上集成平面和非平面CMOS晶体管的过程及其制造
公开(公告)号：WO2007038575A3
公开(公告)日：2007-07-19
申请号：PCT/US2006037634
申请日：2006-09-26
申请人： INTEL CORP , KAVALIEROS JACK , BRASK JUSTIN , DOYLE BRIAN , SHAH UDAY , DATTA SUMAN , DOCZY MARK , METZ MATTHEW , CHAU ROBERT
发明人： KAVALIEROS JACK , BRASK JUSTIN , DOYLE BRIAN , SHAH UDAY , DATTA SUMAN , DOCZY MARK , METZ MATTHEW , CHAU ROBERT
IPC分类号： H01L21/8234 , H01L21/336 , H01L29/10
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar (10) and non-planar (20, 30) transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译：一种能够将平面（10）和非平面（20,30）晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可以在连续的宽度范围内定义。

7. 发明申请

WO2006012338A2 FORMING HIGH-K DIELECTRIC LAYERS ON SMOOTH SUBSTRATES 审中-公开
标题翻译：在平板基板上形成高K介电层
公开(公告)号：WO2006012338A2
公开(公告)日：2006-02-02
申请号：PCT/US2005022573
申请日：2005-06-24
申请人： INTEL CORP , BRASK JUSTIN , KAVALIEROS JACK , DOCZY MARK , METZ MATTHEW , DATTA SUMAN , SHAH UDAY , DEWEY GILBERT , CHAU ROBERT
发明人： BRASK JUSTIN , KAVALIEROS JACK , DOCZY MARK , METZ MATTHEW , DATTA SUMAN , SHAH UDAY , DEWEY GILBERT , CHAU ROBERT
IPC分类号： H01L21/00
CPC分类号： H01L21/02052 , H01L21/28167 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
摘要翻译：可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。在沉积之前，衬底的表面可能被羟基终止物饱和。

8. 发明申请

WO2011090577A3 MULTI-GATE III-V QUANTUM WELL STRUCTURES 审中-公开
标题翻译：多门III-V量子井结构
公开(公告)号：WO2011090577A3
公开(公告)日：2012-02-09
申请号：PCT/US2010059395
申请日：2010-12-08
申请人： INTEL CORP , PILLARISETTY RAVI , KAVALIEROS JACK , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , CHAU ROBERT S , SHAH UDAY , DEWEY GILBERT , RAKSHIT TITASH , METZ MATHEW V
发明人： PILLARISETTY RAVI , KAVALIEROS JACK , MUKHERJEE NILOY , RADOSAVLJEVIC MARKO , CHAU ROBERT S , SHAH UDAY , DEWEY GILBERT , RAKSHIT TITASH , METZ MATHEW V
IPC分类号： H01L21/8238 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42364 , H01L29/66462 , H01L29/66795 , H01L29/7786 , H01L29/785
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括在衬底上形成III-V三栅极翅片，在III-V三栅极鳍周围形成包层材料，并在包层材料周围形成一个Hi k栅极电介质。

9. 发明申请

WO2007002426A2 SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：半导体器件结构和形成半导体结构的方法
公开(公告)号：WO2007002426A2
公开(公告)日：2007-01-04
申请号：PCT/US2006024516
申请日：2006-06-20
申请人： INTEL CORP , BRASK JUSTIN , KAVALIEROS JACK , DOYLE BRIAN , SHAH UDAY , DATTA SUMAN , MAJUMDAR AMLAN , CHAU ROBERT
发明人： BRASK JUSTIN , KAVALIEROS JACK , DOYLE BRIAN , SHAH UDAY , DATTA SUMAN , MAJUMDAR AMLAN , CHAU ROBERT
IPC分类号： H01L21/306 , H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
摘要翻译：对半导体膜的图案化方法进行说明。根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密并且其中所述硬掩模形成在所述第二晶体平面上。接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

10. 发明申请

WO2011075228A2 ISOLATION FOR NANOWIRE DEVICES 审中-公开
标题翻译：纳米器件的隔离
公开(公告)号：WO2011075228A2
公开(公告)日：2011-06-23
申请号：PCT/US2010055225
申请日：2010-11-03
申请人： INTEL CORP , SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
发明人： SHAH UDAY , CHU-KUNG BENJAMIN , JIN BEEN-YIH , PILLARISETTY RAVI , RADOSAVLJEVIC MARKO , RACHMADY WILLY
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译：本公开涉及制造微电子器件的领域。在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构为其上形成微电子结构提供基本上水平的表面。

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