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1. 发明申请

WO2013020051A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL 审中-公开
标题翻译：用于使用注册通道的GAN垂直JFET的方法和系统
公开(公告)号：WO2013020051A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/049520
申请日：2012-08-03
申请人： AVOGY, INC. , KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L29/772
CPC分类号： H01L29/66909 , H01L21/8252 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/66446 , H01L29/66924 , H01L29/8083
摘要： A vertical Ill-nitride field effect transistor includes a drain comprising a first Ill-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second Ill-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third Ill-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical Ill-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.
摘要翻译：垂直III族氮化物场效应晶体管包括：包括第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点，以及包括耦合到漏极的第二III族氮化物材料的漂移区域。场效应晶体管还包括沟道区，该沟道区包括耦合到漏极并沿着垂直方向邻近漏极设置的第三III族氮化物材料，至少部分围绕沟道区的栅极区。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直的氮化物场效应晶体管的工作期间的电流沿着垂直方向，并且沟道区沿第二表面的至少一部分延伸的门区域。

2. 发明申请

WO2013055629A1 METHOD OF FABRICATING A GAN MERGED P-I-N SCHOTTKY (MPS) DIODE 审中-公开
标题翻译：制备GAN MERGED P-I-N肖特基（MPS）二极体的方法
公开(公告)号：WO2013055629A1
公开(公告)日：2013-04-18
申请号：PCT/US2012/059245
申请日：2012-10-08
申请人： AVOGY, INC. , EDWARDS, Andrew P. , NIE, Hui , KIZILYALLI, Isik C. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
发明人： EDWARDS, Andrew P. , NIE, Hui , KIZILYALLI, Isik C. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L21/28
CPC分类号： H01L29/66143 , H01L21/26546 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/08 , H01L29/2003 , H01L29/404 , H01L29/66083 , H01L29/66204 , H01L29/66212 , H01L29/66416 , H01L29/66924 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.
摘要翻译：半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。半导体结构还包括III族氮化物外延结构，其包括耦合到III族氮化物衬底的第一侧的第一III族氮化物外延层和多个第二导电类型的III族氮化物区域。多个III族氮化物区域在多个III族氮化物区域中的每一个之间具有至少一个第一导电类型的III族氮化物外延区域。半导体结构还包括电耦合到多个III族氮化物区域和至少一个III族氮化物外延区域中的一个或多个的第一金属结构。在第一金属结构和至少一个III族氮化物外延区之间产生肖特基接触。

3. 发明申请

WO2014107305A1 METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL TRANSISTOR 审中-公开
标题翻译：氮化钛垂直晶体管的方法和系统
公开(公告)号：WO2014107305A1
公开(公告)日：2014-07-10
申请号：PCT/US2013/076009
申请日：2013-12-18
申请人： AVOGY, INC.
发明人： NIE, Hui , EDWARDS, Andrew P. , KIZILYALLI, Isik , BOUR, David P. , PRUNTY, Thomas P. , DIDUCK, Quentin
IPC分类号： H01L29/808
CPC分类号： H01L29/66462 , H01L21/02389 , H01L21/0254 , H01L29/045 , H01L29/0696 , H01L29/122 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66909 , H01L29/66924 , H01L29/8083
摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
摘要翻译：垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。远端外延层包括源沟道的第一部分，并且相邻图案化的外延层被具有预定距离的间隙分开。垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。近端再生长的外延层包括源通道的第二部分。垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长的外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触。

4. 发明申请

WO2013074291A1 METHOD AND SYSTEM FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS 审中-公开
标题翻译：方法和系统制作烟草材料中的浮动保护环
公开(公告)号：WO2013074291A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/062717
申请日：2012-10-31
申请人： AVOGY, INC.
发明人： DISNEY, Donald R. , EDWARDS, Andrew P. , NIE, Hui , BROWN, Richard J. , KIZILYALLI, Isik C. , BOUR, David P. , ROMANO, Linda , PRUNTY, Thomas R.
IPC分类号： H01L29/06
CPC分类号： H01L21/761 , H01L21/2654 , H01L21/266 , H01L21/765 , H01L29/0619 , H01L29/0642 , H01L29/0692 , H01L29/2003 , H01L29/402 , H01L29/66136 , H01L29/66212 , H01L29/6631 , H01L29/66909 , H01L29/8083 , H01L29/872
摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.
摘要翻译：一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二与第一导电类型相反的第二导电类型的GaN外延层。第二GaN外延层耦合到第一GaN外延层。该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

5. 发明申请

WO2013020061A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN GATE 审中-公开
标题翻译：用于使用注射门的GAN垂直JFET的方法和系统
公开(公告)号：WO2013020061A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/049549
申请日：2012-08-03
申请人： AVOGY, INC. , KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L29/66
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/1095 , H01L29/2003 , H01L29/66446 , H01L29/66909 , H01L29/66924
摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
摘要翻译：垂直III族氮化物场效应晶体管包括：包含第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点;以及漂移区域，包括耦合到漏极并邻近漏极设置的第二III族氮化物材料垂直方向场效应晶体管还包括沟道区，该沟道区包括耦合到漂移区的第三III族氮化物材料，至少部分围绕沟道区的栅极区和电耦合到栅极区的栅极接触。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物场效应晶体管的工作期间的电流沿垂直方向。

6. 发明申请

WO2014107304A1 GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE 审中-公开
标题翻译：具有六角形细胞结构的硝酸锌垂直JFET
公开(公告)号：WO2014107304A1
公开(公告)日：2014-07-10
申请号：PCT/US2013/076007
申请日：2013-12-18
申请人： AVOGY, INC.
发明人： EDWARDS, Andrew P. , NIE, Hui , DISNEY, Donald R. , KIZILYALLI, Isik
IPC分类号： H01L29/15
CPC分类号： H01L27/098 , H01L29/0692 , H01L29/2003 , H01L29/42312 , H01L29/66909 , H01L29/8083
摘要： An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.
摘要翻译： GaN基垂直JFET的阵列包括包含一个或多个JFET的漏极和耦合到GaN衬底的一个或多个外延层的GaN衬底。该阵列还包括耦合到一个或多个外延层并沿垂直于GaN衬底的方向延伸的多个六边形单元。多个六边形单元的侧壁相对于GaN衬底的晶面基本上对齐。阵列还包括多个通道区域，每个沟道区域具有邻近多个六边形单元的侧壁的部分，一个或多个JFET的多个栅极区域，每个栅极区域电耦合到多个沟道区域中的一个或多个以及电耦合到多个沟道区中的一个或多个的一个或多个JFET的多个源极区。

7. 发明申请

WO2013096013A1 METHOD OF FABRICATING A GALLIUM NITRIDE P-I-N DIODE USING IMPLANTATION 审中-公开
标题翻译：使用植入制备氮化镓P-I-N二极体的方法
公开(公告)号：WO2013096013A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/068972
申请日：2012-12-11
申请人： AVOGY, INC.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , BROWN, Richard J. , DISNEY, Donald R.
IPC分类号： H01L31/112
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0649 , H01L29/2003 , H01L29/66204 , H01L29/66212 , H01L29/6631 , H01L29/66924
摘要： A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region
摘要翻译： III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

8. 发明申请

WO2013066967A1 MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE 审中-公开
标题翻译：单相整体垂直JFET和肖特基二极管
公开(公告)号：WO2013066967A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/062728
申请日：2012-10-31
申请人： AVOGY, INC.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/0605 , H01L27/0611 , H01L27/0629 , H01L27/0727 , H01L27/098 , H01L29/2003 , H01L29/66143 , H01L29/8083 , H01L29/872
摘要： An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.
摘要翻译：包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区，以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。集成器件还包括至少部分地围绕沟道区的栅极区，耦合到沟道区的源极和耦合到漂移区的肖特基接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

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