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1. 发明申请

WO1995008221A1 DIGITAL TO ANALOG CONVERSION USING NONUNIFORM SAMPLE RATES 审中-公开
标题翻译：数字模拟转换使用非统计量样本率
公开(公告)号：WO1995008221A1
公开(公告)日：1995-03-23
申请号：PCT/US1994010269
申请日：1994-09-13
申请人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A. , SOBOL, James, M.
发明人： ANALOG DEVICES, INC.
IPC分类号： H03M01/66
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50 , H03M3/372 , H03M3/50
摘要： A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator.
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。在一个实施例中，数字数据被内插固定比率，然后在Σ-Δ调制频率选择信号的控制下抽取，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率。在另一个实施例中，数字数据在Σ-Δ调制频率选择信号的控制下进行内插，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率，然后以固定比率抽取。使用第n级m位Σ-Δ调制器来调制频率信号选择数。因此，数据因此在第n级m位Σ-Δ调制器的时钟速率下从内插/抽取处理中出现。该方法和装置将输入的数字数据流的数据速率转换为第n阶m位Σ-Δ调制器的数据速率。

2. 发明申请

WO1995031860A1 DIGITAL-TO-DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES 审中-公开
标题翻译：数字到数字转换使用非统计量样本率
公开(公告)号：WO1995031860A1
公开(公告)日：1995-11-23
申请号：PCT/US1995003739
申请日：1995-03-23
申请人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A. , SOBOL, James, M.
发明人： ANALOG DEVICES, INC.
IPC分类号： H03H17/06
CPC分类号： H03H17/0628 , H03H17/0614 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50
摘要： A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio. In another embodiment, the digital data is interpolated under control of a first sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. Thereafter, the digital data is interpolated by a fixed ratio and then decimated under control of a second sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the first n-th m-bit sigma-delta modulator and then converts the digital data stream from the first sigma-delta modulator (20) to an output data rate determined by the second n-th order m-bit sigma-delta modulator (32).
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由不均匀采样产生的噪声被频率形成为可以通过常规滤波技术去除的区域（即，移位到较高频率）。在一个实施例中，数字数据以固定比例内插（16），然后在第一Σ-Δ调制频率选择信号（26）的控制下抽取（21），平均来说代表输入数字数据的数据速率流。此后，数字数据在第二Σ-Δ调制频率选择信号（46）的控制下被内插（30），第二Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后抽取（40）按固定比例。在另一实施例中，数字数据在第一Σ-Δ调制频率选择信号的控制下进行内插，该第一Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率，然后以固定比率抽取。此后，数字数据以固定比例内插，然后在第二Σ-Δ调制频率选择信号的控制下抽取，该第二Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。第一和第二频率信号选择号码使用n阶m位Σ-Δ调制器进行调制。该方法和装置将输入数字数据流的数据速率转换为第一n位m位Σ-Δ调制器的数据速率，然后将来自第一Σ-Δ调制器（20）的数字数据流转换为由第二n位m位Σ-Δ调制器（32）确定的输出数据速率。

3. 发明申请

WO1995008220A1 ANALOG TO DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES 审中-公开
标题翻译：模拟数字转换使用非统计量样本率
公开(公告)号：WO1995008220A1
公开(公告)日：1995-03-23
申请号：PCT/US1994010268
申请日：1994-09-13
申请人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A. , SOBOL, James, M.
发明人： ANALOG DEVICES, INC.
IPC分类号： H03M01/12
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50 , H03M3/498
摘要： A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。在另一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下被抽取，该Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。使用第n级m位Σ-Δ调制器调制频率选择信号。数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

4. 发明申请

WO1997045998A2 METHOD AND APPARATUS FOR TIME SHARED FINITE IMPULSE RESPONSE FILTER WITH MULTIPLE SIGNAL STREAM CAPABILITY 审中-公开
标题翻译：具有多个信号流能力的时间共享有限冲击响应滤波器的方法和装置
公开(公告)号：WO1997045998A2
公开(公告)日：1997-12-04
申请号：PCT/US1997009141
申请日：1997-05-30
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , MURRAY, Brian, P. , CURRAN, Philip, A. , PRENDERGAST, Colm, J. , CUMMINS, Timothy, J.
IPC分类号： H04N00/00
CPC分类号： H03H17/06 , H04N7/0102 , H04N9/64
摘要： A novel finite impulse response filter apparatus and method are disclosed. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operators are connected to and odd taps and even weight and sum operators are connected to the odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.
摘要翻译：公开了一种新颖的有限脉冲响应滤波器装置和方法。提供由两个或多个数据流组成的复用数据流作为抽头延迟线的输入。重量和和运算符连接到偶数或奇数延迟线抽头，并生成滤波输出。滤波器对每个周期的一个数据流进行操作，并产生多路输出。在另一种形式中，奇数和和运算符连接到奇数抽头，甚至重量和和运算符连接到产生两个滤波输出的奇数抽头。滤波器在每个周期中对两个数据流进行操作，并生成两个多路复用输出。公开了一种用于将多路复用输出解析为组成滤波数据流的交叉开关。过滤器级可以级联。

5. 发明申请

WO1997029546A1 REFERENCE VOLTAGE CIRCUIT 审中-公开
标题翻译：参考电压电路
公开(公告)号：WO1997029546A1
公开(公告)日：1997-08-14
申请号：PCT/US1997001674
申请日：1997-02-11
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , SHERRY, Adrian , MCCARTNEY, Damien
IPC分类号： H03M01/06
CPC分类号： H03M1/1076 , H03M1/12
摘要： An invalid reference detection circuit (10) is formed on a semiconductor chip having reference input terminals adapted for coupling to a reference source (12) external to the chip, a local reference source (14), and comparison circuit (15). The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and produce an output signal (17) indicative of the condition. The invalid condition at the reference input terminals may be an open circuit, a voltage across the reference input terminals being below a predetermined minimum or above a predetermined maximum, and/or short circuit. An analog/digital conversion system (8) is formed on a semiconductor chip together with the invalid reference detection circuit. The reference input terminals are adapted for coupling to the conversion circuitry.
摘要翻译：在具有参考输入端子的半导体芯片上形成无效参考检测电路（10），该参考输入端子适于与芯片外部的参考源（12）耦合，本地参考源（14）和比较电路（15）。比较电路响应于本地参考源和参考输入端子处的条件，以检测参考输入端子处的无效状态，并产生指示条件的输出信号（17）。在参考输入端子处的无效状态可以是开路，参考输入端子两端的电压低于预定最小值或高于预定最大值，和/或短路。模拟/数字转换系统（8）与无效参考检测电路一起形成在半导体芯片上。参考输入端适于耦合到转换电路。

6. 发明申请

WO1997020396A2 POTS SPLITTER ASSEMBLY WITH IMPROVED TRANSHYBRID LOSS FOR DIGITAL SUBSCRIBER LOOP TRANSMISSION 审中-公开
标题翻译： POTS分线器组件与改进的数字用户链路传输的变速箱损失
公开(公告)号：WO1997020396A2
公开(公告)日：1997-06-05
申请号：PCT/US1996018682
申请日：1996-11-20
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , RUSSELL, Mark, A. , RIBNER, David, B.
IPC分类号： H04B00/00
CPC分类号： H04M11/062 , H04Q2213/13034 , H04Q2213/13174 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13305 , H04Q2213/1332
摘要： A data transmission system including a telephone service subscriber loop utilized for transmission of data including telephone service signals; a splitter operable for splitting the subscriber loop into a first transmission path including a low pass filter which accommodates a continuation of telephone service signal transmissions along the subscriber loop and a second transmission path, said second transmission path including a capacitive element for attenuating the telephone service signals; and a digital subscriber loop transceiver coupled to the second transmission path for implementing high rate digital data transmission over the subscriber loop, the transceiver including a frontend processing circuit having a transmit path and a receive path, at least said receive path comprising a high pass filter for further attenuating said telephone service signals. The capacitive element in the second transmission path and the high pass filter in the receive path of the transceiver frontend operate in conjunction to maintain transhybrid loss.
摘要翻译：一种数据传输系统，包括用于传输包括电话业务信号的数据的电话业务用户环路; 分离器，其可操作用于将所述用户环路分解成包括低通滤波器的第一传输路径，所述低通滤波器容纳沿着所述用户环路和第二传输路径的电话服务信号传输的延续，所述第二传输路径包括用于衰减所述电话服务信号; 耦合到第二传输路径的数字用户环路收发机，用于通过用户环路实现高速率数字数据传输，该收发器包括具有发射路径和接收路径的前端处理电路，至少所述接收路径包括高通滤波器用于进一步衰减所述电话服务信号。第二传输路径中的电容元件和收发器前端的接收路径中的高通滤波器一起工作，以保持变压器损耗。

7. 发明申请

WO1997012442A1 IMPROVED GATE DRIVER CIRCUIT AND HYSTERESIS CIRCUIT THEREFOR 审中-公开
标题翻译：改进的门驱动电路及其滞后电路
公开(公告)号：WO1997012442A1
公开(公告)日：1997-04-03
申请号：PCT/US1996014429
申请日：1996-09-11
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , GOEL, Rakesh
IPC分类号： H03K03/037
CPC分类号： H03K3/2893 , H03K17/063 , H03K17/6871
摘要： A hysteresis circuit including first (88) and second (90) voltage reference circuits responsive to an input control signal ((VA) for providing first and second voltage levels connected in series to produce a higher voltage level; a first switching circuit (82), responsive to the voltage reference circuits to turn on and provide an output drive signal when the higher voltage is reached; a second switching circuit (84), responsive to the first switching circuit turning on, for removing one of the first and second voltage levels to produce a lower voltage level; the first switching circuit turning off in response to the input level control signal decreasing below the lower voltage level.
摘要翻译：响应于用于提供串联连接以产生较高电压电平的第一和第二电压电平的输入控制信号（（VA）），包括第一（88）和第二（90）电压参考电路的滞后电路;第一开关电路（82）响应于所述电压参考电路导通并在达到较高电压时提供输出驱动信号;第二开关电路（84），响应于所述第一开关电路导通，用于去除所述第一和第二电压电平之一以产生较低的电压电平;第一开关电路响应于输入电平控制信号降低到较低电压电平以下而关断。

8. 发明申请

WO1997012402A1 SEMICONDUCTOR CHARGE POTENTIAL WELLS WITH INTEGRATED DIFFUSIONS 审中-公开
标题翻译：具有集成扩散的半导体充电电位阱
公开(公告)号：WO1997012402A1
公开(公告)日：1997-04-03
申请号：PCT/US1996015285
申请日：1996-09-24
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , MUNROE, Scott, C.
IPC分类号： H01L29/768
CPC分类号： H01L29/76816 , H01L29/42396 , H01L29/768 , H01L29/772 , H01L29/7831 , H01L29/94
摘要： A semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer (40) provided on the semiconductor region; a gate electrode (32, 34, 38) provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion (36) of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer (40), the diffusion (36) being in direct ohmic contact with the potential well. The diffusion (36) can be either a n+ or p+ diffusion. The diffusion (36) accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.
摘要翻译：一种半导体器件，具有包括第一预定导电类型的材料的半导体区域; 设置在所述半导体区域上的绝缘层（40）设置在所述绝缘层上的栅极电极，所述栅极电极响应于施加到所述栅电极的电位而在所述半导体区域内形成势阱; 并且第二预定导电类型的高掺杂材料的扩散（36）位于半导体区域内，并且通过栅电极和绝缘层（40）中的开口施加，扩散（36）直接欧姆接触势阱。扩散（36）可以是n +或p +扩散。扩散（36）可以减少潜在井内的电荷再分配的横向时间常数，直接感测井中的电荷，以及向井和从井的注入和提取电荷。

9. 发明申请

WO1997009790A1 A DECIMATING PRML SIGNAL PROCESSOR SYSTEM 审中-公开
标题翻译： DECIMATING PRML信号处理器系统
公开(公告)号：WO1997009790A1
公开(公告)日：1997-03-13
申请号：PCT/US1996002743
申请日：1996-03-01
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , HITCHCOX, David , SHEPHERD, Paul
IPC分类号： H03M13/00
CPC分类号： H03H21/0012 , G11B20/10009 , H03H17/0664 , H04L7/0062 , H04L7/10
摘要： A decimating PRML signal processor system (10) for processing a PRML data signal includes: an adaptive filter circuit (22) for receiving and for shaping the data signal; a gain control circuit (30), responsive to the adaptive filter circuit (22), for adjusting the gain of the data signal; a phase control circuit (32), responsive to the adaptive filter circuit (22), for adjusting the phase of the data signal; a clock circuit (40) for providing signals for driving each of the circuits; and a decimation controller (42) for reducing the rate of the clock signals to at least one of the circuits to decrease the power required to operate the system.
摘要翻译：用于处理PRML数据信号的抽取PRML信号处理器系统（10）包括：自适应滤波器电路（22），用于接收和整形数据信号; 响应于所述自适应滤波器电路（22）的增益控制电路（30），用于调整所述数据信号的增益; 响应于所述自适应滤波器电路（22）的相位控制电路（32），用于调整所述数据信号的相位; 时钟电路（40），用于提供用于驱动每个电路的信号; 以及抽取控制器（42），用于将时钟信号的速率降低到至少一个电路以降低操作系统所需的功率。

10. 发明申请

WO1996041413A1 LINEAR-IN-DECIBEL VARIABLE GAIN AMPLIFIER 审中-公开
标题翻译：线性可变增益放大器
公开(公告)号：WO1996041413A1
公开(公告)日：1996-12-19
申请号：PCT/US1996009977
申请日：1996-06-06
申请人： ANALOG DEVICES, INC. , GILBERT, Barrie
发明人： ANALOG DEVICES, INC.
IPC分类号： H03F03/45
CPC分类号： H03G7/06 , H03G7/001
摘要： A gain control circuit (22) provides linear-in-decibel gain control for an RF signal variable gain amplifier (12). The gain control circuit (22) utilizes the transconductance characteristics of bipolar transistors to generate a logarithmic relationship betweena gain control current (IG) and an amplifier bias current (IC). The gain control circuit (22) comprises essentially a current mirror having two transistors (Q1, Q2) with a resistor (R1) coupled between the associated base terminals of the two transistors (Q1, Q2). A third transistor (Q3) and a resistor (R2) are also provided to absorb the gain control current (IG). The gain control current (IG) is applied to a base of a first one (Q1) of the two transistors and a voltage is thereby established across the resistor. This voltage subtracts from the base-emitter voltage of the second transistor (Q2) thereby producing a corresponding exponential reduction in the current through the second transistor (Q2). This current (IC) is provided to a gm stage (12), whose gain is linearly proportional to this current. Thus, a linear change in the gain control current (IG) produces an exponential change in the gainof the gm stage (12). Accordingly, a linear-in dB variable gain amplifier is achieved.
摘要翻译：增益控制电路（22）为RF信号可变增益放大器（12）提供线性分贝增益控制。增益控制电路（22）利用双极晶体管的跨导特性产生增益控制电流（IG）和放大器偏置电流（IC）之间的对数关系。增益控制电路（22）基本上包括具有两个晶体管（Q1，Q2）的电流镜，电阻器（R1）耦合在两个晶体管（Q1，Q2）的相关联的基极之间。还提供第三晶体管（Q3）和电阻器（R2）以吸收增益控制电流（IG）。增益控制电流（IG）被施加到两个晶体管的第一个（Q1）的基极，并且由此在电阻器两端形成电压。该电压从第二晶体管（Q2）的基极 - 发射极电压减去，从而产生通过第二晶体管（Q2）的电流的相应的指数减小。该电流（IC）被提供给gm级（12），其增益与该电流成线性比例。因此，增益控制电流（IG）的线性变化产生gm级（12）的增益的指数变化。因此，实现了线性dB的可变增益放大器。

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