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1. 发明申请

WO1995031860A1 DIGITAL-TO-DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES 审中-公开
标题翻译：数字到数字转换使用非统计量样本率
公开(公告)号：WO1995031860A1
公开(公告)日：1995-11-23
申请号：PCT/US1995003739
申请日：1995-03-23
申请人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A. , SOBOL, James, M.
发明人： ANALOG DEVICES, INC.
IPC分类号： H03H17/06
CPC分类号： H03H17/0628 , H03H17/0614 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50
摘要： A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio. In another embodiment, the digital data is interpolated under control of a first sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. Thereafter, the digital data is interpolated by a fixed ratio and then decimated under control of a second sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the first n-th m-bit sigma-delta modulator and then converts the digital data stream from the first sigma-delta modulator (20) to an output data rate determined by the second n-th order m-bit sigma-delta modulator (32).
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由不均匀采样产生的噪声被频率形成为可以通过常规滤波技术去除的区域（即，移位到较高频率）。在一个实施例中，数字数据以固定比例内插（16），然后在第一Σ-Δ调制频率选择信号（26）的控制下抽取（21），平均来说代表输入数字数据的数据速率流。此后，数字数据在第二Σ-Δ调制频率选择信号（46）的控制下被内插（30），第二Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后抽取（40）按固定比例。在另一实施例中，数字数据在第一Σ-Δ调制频率选择信号的控制下进行内插，该第一Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率，然后以固定比率抽取。此后，数字数据以固定比例内插，然后在第二Σ-Δ调制频率选择信号的控制下抽取，该第二Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。第一和第二频率信号选择号码使用n阶m位Σ-Δ调制器进行调制。该方法和装置将输入数字数据流的数据速率转换为第一n位m位Σ-Δ调制器的数据速率，然后将来自第一Σ-Δ调制器（20）的数字数据流转换为由第二n位m位Σ-Δ调制器（32）确定的输出数据速率。

2. 发明申请

WO9628889A3 DIGITAL PHASE-LOCKED LOOP UTILIZING A HIGH ORDER SIGMA-DELTA MODULATOR 审中-公开
标题翻译：使用高阶SIGMA-DELTA调制器的数字相位锁定环
公开(公告)号：WO9628889A3
公开(公告)日：1996-10-24
申请号：PCT/US9603205
申请日：1996-03-06
申请人： ANALOG DEVICES INC
发明人： WILSON JAMES , CELLINI RONALD A
IPC分类号： H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M1/12 , H03M3/02 , H03M7/36 , H03L7/113
CPC分类号： H03H17/0614 , H03H17/0657 , H03H17/0664 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50 , H03M7/3022
摘要： A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.

3. 发明申请

WO2006124060A2 SAMPLE RATE CONVERSION MODULE AND APPLICATIONS THEREOF 审中-公开
标题翻译：采样率转换模块及其应用
公开(公告)号：WO2006124060A2
公开(公告)日：2006-11-23
申请号：PCT/US2005/039281
申请日：2005-10-31
申请人： SIGMATEL, INC.
发明人： MAY, Michael, R.
IPC分类号： H04L27/06
CPC分类号： H04L25/05 , H03H17/0286 , H03H17/0614 , H03H17/0621 , H04L27/142 , H04L2027/0024 , H04L2027/0087
摘要： A sample rate converter includes an upsampling module, a low pass filter, and a linear sample rate conversion module. The upsampling module is operably coupled up-sample a digital input signal having a first rate to produce a digitally up-sampled signal. The low pass filter is operably coupled to low pass filter the digitally up-sampled signal to produce a digitally filtered signal at an up-sampled rate. The linear sample rate conversion module is operably coupled to convert the digitally up-sampled signal into a sample rate adjusted digital signal having a second rate based on an control feedback signal and a linear function, wherein a relationship between the first rate and the second rate is a nonpower of two.
摘要翻译：采样率转换器包括上采样模块，低通滤波器和线性采样率转换模块。上采样模块可操作地耦合上采样具有第一速率的数字输入信号以产生数字上采样信号。低通滤波器可操作地耦合到低通滤波器数字上采样信号，以产生以上采样速率的数字滤波信号。线性采样率转换模块可操作地耦合以将数字上采样信号转换为基于控制反馈信号和线性函数的具有第二速率的采样率调整数字信号，其中第一速率与第二速率之间的关系是一个非权力的两个。

4. 发明申请

WO2005015752A3 NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD 审中-公开
标题翻译：噪声形状的插值器和减法器装置和方法
公开(公告)号：WO2005015752A3
公开(公告)日：2005-03-24
申请号：PCT/US2004025323
申请日：2004-08-04
申请人： ST MICROELECTRONICS INC
发明人： NORSWORTHY STEVEN R , REDGRAVE JASON RUPERT
IPC分类号： H03H17/06 , H04B20060101 , H04L27/10
CPC分类号： H03H17/0628 , G06F5/14 , G06F2205/061 , H03H17/0614
摘要： Improved interpolator (1304) and decimator (1324) apparatus and methods, including the addition of an elastic storage element (192) comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified imterpolator and decimator.
摘要翻译：改进的内插器（1304）和抽取器（1324）的装置和方法，包括添加弹性存储元件（192）包括有利地允许采样时钟的短期变化被吸收的FIFO，并且还提供用于控制 delta-sigma调制模N计数器采样时钟发生器。与Δ-Σ调制器和计数器组合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的仿真器和抽取器。

5. 发明申请

WO1996028889A2 DIGITAL PHASE-LOCKED LOOP UTILIZING A HIGH ORDER SIGMA-DELTA MODULATOR 审中-公开
标题翻译：使用高阶SIGMA-DELTA调制器的数字相位锁定环
公开(公告)号：WO1996028889A2
公开(公告)日：1996-09-19
申请号：PCT/US1996003205
申请日：1996-03-06
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A.
IPC分类号： H03L07/113
CPC分类号： H03H17/0614 , H03H17/0657 , H03H17/0664 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50 , H03M7/3022
摘要： A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.
摘要翻译：一种用于相位锁定到输入信号并输出Σ-Δ调制控制信号的方法和装置。本发明的方法和装置提供了一种Σ-Δ调制控制信号，其可由抽取器中的任何一个利用，以第一数据速率将数字数据以第二数据速率抽取数字数据，以及用于内插的内插器以第一数据速率将数字数据以第二数据速率传送到数字数据。抽头和内插器可用于模数转换器，数 - 模转换器和数 - 数转换器中的任何一个。在一个实施例中，确定输入信号的周期并将其馈送到锁相环，该锁相环包括用于提供Σ-Δ调制控制信号的Σ-Δ调制器。锁相环还包括用于确定输入信号和由锁相环产生的转换信号之间的相位和频差的相位检测器。因此，该方法和装置锁定到输入信号的相位和频率，并提供锁相Σ-Δ调制控制信号。

6. 发明申请

WO1995008220A1 ANALOG TO DIGITAL CONVERSION USING NONUNIFORM SAMPLE RATES 审中-公开
标题翻译：模拟数字转换使用非统计量样本率
公开(公告)号：WO1995008220A1
公开(公告)日：1995-03-23
申请号：PCT/US1994010268
申请日：1994-09-13
申请人： ANALOG DEVICES, INC. , WILSON, James , CELLINI, Ronald, A. , SOBOL, James, M.
发明人： ANALOG DEVICES, INC.
IPC分类号： H03M01/12
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03L2207/50 , H03M3/498
摘要： A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。在另一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下被抽取，该Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。使用第n级m位Σ-Δ调制器调制频率选择信号。数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

7. 发明申请

WO2008005151A8 DIGITAL NON-INTEGER SAMPLE/HOLD IMPLEMENTED USING VIRTUAL FILTERING 审中-公开
标题翻译：使用虚拟过滤实现的数字非整数样本/保持
公开(公告)号：WO2008005151A8
公开(公告)日：2008-06-05
申请号：PCT/US2007013608
申请日：2007-06-08
申请人： CIRRUS LOGIC INC
发明人： DING LEI , MELANSON JOHN L , FEI XIAOFAN , DUEWER BRUCE
IPC分类号： H03H17/06
CPC分类号： H03H17/0685 , H03H17/0275 , H03H17/0614

8. 发明申请

WO2006003583A1 POLYPHASE INTERPOLATING FILTER WITH NOISE SHAPING MODULATOR 审中-公开
标题翻译：带有噪声调制器的多相插值滤波器
公开(公告)号：WO2006003583A1
公开(公告)日：2006-01-12
申请号：PCT/IB2005/052100
申请日：2005-06-24
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DE BUYS, Frans, V., F.
发明人： DE BUYS, Frans, V., F.
IPC分类号： H03H17/06
CPC分类号： H03H17/0628 , H03H17/0275 , H03H17/0614
摘要： A polyphase filtering method and a polyphase filter is described having N polyphase branches, which receives input samples, an a single branch of the polyphase filter is selected for an interpolation of an input sample. A noise shaping modulator is used for noise shaping the output of the filter to thereby reduce the noise error introduced by selecting only the one single branch of the polyphase filter. The advantages of the filter and method according to the present invention are: The system can be cheaper to implement, depending on the order of the noise shaper needed to obtain sufficient performance. The system can have the same performance as conventional systems with lower over sampling factors, due to the lack of a linear distribution, and as such use less memory.
摘要翻译：描述了多相滤波方法和多相滤波器，其具有接收输入样本的N个多相分支，选择多相滤波器的单个分支用于输入样本的插值。噪声整形调制器用于对滤波器的输出进行噪声整形，从而减少仅通过选择多相滤波器的单个分支引入的噪声误差。根据本发明的过滤器和方法的优点是：根据获得足够性能所需的噪声整形器的顺序，该系统可以实现更便宜。由于缺乏线性分布，系统可以具有与具有较低采样因子的常规系统相同的性能，因此使用较少的存储器。

9. 发明申请

WO2005015752A8 NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD 审中-公开
标题翻译：噪声形状的插入器和分离器装置和方法
公开(公告)号：WO2005015752A8
公开(公告)日：2005-07-07
申请号：PCT/US2004025323
申请日：2004-08-04
申请人： ST MICROELECTRONICS INC
发明人： NORSWORTHY STEVEN R , REDGRAVE JASON RUPERT
IPC分类号： H03H17/06 , H04B20060101 , H04L27/10
CPC分类号： H03H17/0628 , G06F5/14 , G06F2205/061 , H03H17/0614
摘要： Improved interpolator (1304) and decimator (1324) apparatus and methods, including the addition of an elastic storage element (192) comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified imterpolator and decimator.
摘要翻译：包括添加弹性存储元件（192）的改进的内插器（1304）和抽取器（1324）设备和方法包括有利地允许吸收采样时钟中的短期变化的FIFO，并且还提供用于控制 Δ-Σ调制的基于模N计数器的采样时钟发生器。与delta-sigma调制器和计数器组合在一起的弹性元件创建了一个噪音形状的频率锁定环，无需额外的元件，从而得到简化的插入器和抽取器。

10. 发明申请

WO01010024A1 CIRCUIT FOR CONVERTING THE SCANNING RATE CONVERSION OF CHRONOLOGICALLY DISCRETE SIGNALS 审中-公开
标题翻译：电路中采样实施时间离散信号
公开(公告)号：WO01010024A1
公开(公告)日：2001-02-08
申请号：PCT/DE2000/002509
申请日：2000-07-28
IPC分类号： H03H17/06
CPC分类号： H03H17/0614 , H03H17/0621
摘要： Disclosed is a circuit for converting chronologically discrete scanning rate signals which are fed to a scanning rate signal converter, which, after application of an approximation procedure, is used to convert feed input signals to output signals having a different scanning rate. A clocked pulse generator matches the output scanning frequency with the input scanning frequency; said clocked pulse generator (T) is controlled by a sigma-delta-modulator (M) which converts the major part of the approximation error signal to high frequencies.
摘要翻译：在用于采样率转换，其被提供给采样速率转换器时间离散信号，使用从提供给它的输入信号的近似方法，其形成不同的采样率的输出信号的电路装置，一个时钟发生器调整输入采样频率，时钟发生器的输出采样频率（T）与形成由在高频率近似误差信号所得到的主要部分的Σ-Δ调制器控制的（M）。

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