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1. 发明申请

WO2021133419A1 PACKAGING PROCESS FOR SIDE-WALL PLATING WITH A CONDUCTIVE FILM 审中-公开
公开(公告)号：WO2021133419A1
公开(公告)日：2021-07-01
申请号：PCT/US2020/017131
申请日：2020-02-07
申请人： VISHAY GENERAL SEMICONDUCTOR, LLC
发明人： JIN, Longnan , KARRER, Heinrich , LIU, Junfeng , DING, Huiying , SCHMIDT, Thomas
IPC分类号： H01L21/56 , H01L23/28 , H01L23/495
摘要： Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.

2. 发明申请

WO2014077862A1 GAN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE 审中-公开
标题翻译：基于GAN的肖特基二极管具有部分残留阳极
公开(公告)号：WO2014077862A1
公开(公告)日：2014-05-22
申请号：PCT/US2012/071621
申请日：2012-12-26
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： LIN, Yih-Yin
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/205 , H01L29/417 , H01L29/66212
摘要： A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.
摘要翻译：提供了诸如肖特基二极管的半导体器件，其包括衬底，设置在衬底上的第一有源层和设置在第一有源层上的第二有源层。第二有源层具有比第一有源层更高的带隙，使得在第一有源层和第二有源层之间产生二维电子气层。第一电极具有设置在第二有源层的凹部中的第一部分和设置在第二有源层上的第二部分，从而与其形成肖特基结。第二电极与第一有源层接触。第二电极与第一有源层建立欧姆结。

3. 发明申请

WO2014077860A1 GaN-BASED SCHOTTKY DIODE HAVING DUAL METAL, PARTIALLY RECESSED ELECTRODE 审中-公开
标题翻译：具有双金属，部分电极的GaN基肖特基二极管
公开(公告)号：WO2014077860A1
公开(公告)日：2014-05-22
申请号：PCT/US2012/071005
申请日：2012-12-20
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： LIN, Yih-Yin
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/205 , H01L29/417 , H01L29/475 , H01L29/66143 , H01L29/66212 , H01L29/778 , H01L29/7786
摘要： A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer
摘要翻译：半导体器件包括衬底，设置在衬底上的第一有源层和设置在第一有源层上的第二有源层。第二有源层具有比第一有源层更高的带隙，使得在第一有源层和第二有源层之间产生二维电子气层。第一电极具有设置在第二有源层的凹部中的第一部分和设置在第二有源层上的第二部分，从而与其形成肖特基结。第一电极的第一部分具有比第一电极的第二部分更低的肖特基势垒。第二电极与第一有源层接触。第二电极与第一有源层建立欧姆结

4. 发明申请

WO2012054686A2 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 审中-公开
标题翻译：带有改进的终端结构的高电压应用的沟槽式DMOS器件
公开(公告)号：WO2012054686A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057020
申请日：2011-10-20
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-Wei , UDREA, Florin , LIN, Yih-Yin
发明人： HSU, Chih-Wei , UDREA, Florin , LIN, Yih-Yin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/063 , H01L29/0661 , H01L29/407 , H01L29/66143 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.
摘要翻译：用于功率晶体管的终端结构包括具有有源区和终端区的半导体衬底。衬底具有第一类型的导电性。终止沟槽位于终止区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。掺杂区域具有设置在终止沟槽下方的衬底中的第二类型的导电性。 MOS栅极形成在与边界相邻的侧壁上。掺杂区域从与边界间隔开的MOS栅极的一部分的下方朝向终端沟槽的远端侧壁延伸。端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并且朝向衬底的边缘延伸。第一导电层形成在半导体衬底的背侧表面上。第二导电层形成在MOS栅极的暴露部分的有源区顶上，并且延伸以覆盖终止结构氧化物层的至少一部分。

5. 发明申请

WO2012054682A2 IMPROVED SCHOTTKY RECTIFIER 审中-公开
标题翻译：改进的肖特基整流器
公开(公告)号：WO2012054682A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057012
申请日：2011-10-20
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
发明人： HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
IPC分类号： H01L29/872 , H01L29/868 , H01L21/329
CPC分类号： H01L29/66143 , H01L21/22 , H01L21/265 , H01L29/0619 , H01L29/872 , H01L29/8725
摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
摘要翻译：半导体整流器包括具有第一类导电性的半导体衬底。形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。第一电极形成在金属层的上方，第二电极形成在基板的背面。

6. 发明申请

WO2011115775A1 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 审中-公开
标题翻译： TRENCH DMOS器件具有改进的高压应用终止结构
公开(公告)号：WO2011115775A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/027464
申请日：2011-03-08
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
发明人： HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/0615 , H01L29/0661 , H01L29/404 , H01L29/66143 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MaS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion ofthe MaS gate spaced apart from the boundary toward the edge ofthe semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MaS gate and extends toward the edge of the substrate.
摘要翻译：为功率晶体管提供端接结构。端接结构包括具有有源区和端接区的半导体衬底。衬底具有第一类导电性。终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 MaS门形成在与边界相邻的侧壁上。掺杂区域从距离边界的半导体衬底的边缘间隔开的MaS栅极的一部分的下方延伸。端接结构氧化物层形成在覆盖MaS栅极的一部分并且朝向衬底边缘延伸的端接沟槽上。

7. 发明申请

WO2008045177A3 ELECTRONIC DEVICE AND LEAD FRAME 审中-公开
公开(公告)号：WO2008045177A3
公开(公告)日：2008-04-17
申请号：PCT/US2007/019946
申请日：2007-09-14
申请人： VISHAY GENERAL SEMICONDUCTOR, LLC , CHOU, Peter , TIAN, Lucy , ZHANG, Bear
发明人： CHOU, Peter , TIAN, Lucy , ZHANG, Bear
IPC分类号： H01L21/58 , H01L21/60 , H01L23/495
摘要： A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive a die, is associated with each structure. When dies are disposed on the receiving surfaces, anodes are similarly-oriented. A number of fingers are attached to the lead frame, and one or more electrode contact surfaces are attached to each finger. Each electrode contact surface can be positioned (for example, bent) with respect to one receiving surface, to facilitate electrical connection between the anode of a die and a iead. The lead frame may be used in connection with surface- and through-hole-mountable electronic devices, such as bridge rectifier modules.

8. 发明申请

WO2008042096A3 HIGH BREAKDOWN VOLTAGE DIODE AND METHOD OF FORMING SAME 审中-公开
公开(公告)号：WO2008042096A3
公开(公告)日：2008-04-10
申请号：PCT/US2007/019947
申请日：2007-09-14
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , KAO, Lung-Ching , KUNG, Pu-Ju
发明人： KAO, Lung-Ching , KUNG, Pu-Ju
IPC分类号： H01L29/72
摘要： A multiple layer overvoltage protection device is provided. The method begins by providing a substrate having a first impurity concentration of a first conductivity type to define a mid-region layer. A dopant of a second conductivity type is introduced into the substrate with a second impurity concentration less than the first impurity concentration. An upper base region having a second type of conductivity is formed on the upper surface of the mid-region layer. A lower base region layer having a second type of conductivity is formed on a lower surface of the mid-region layer. A first emitter region having a first type of conductivity is formed on a surface of the upper base region layer. A first metal contact is coupled to the upper base region layer and a second metal contact is coupled to the lower base region layer.

9. 发明申请

WO2008021220A3 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT DISSIPATION CAPABILITIES 审中-公开
公开(公告)号：WO2008021220A3
公开(公告)日：2008-02-21
申请号：PCT/US2007/017768
申请日：2007-08-10
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , CHOU, Ta-Te , ZHANG, Xiong-Jie , LI, Xian , FU, Hai , TIAN, Yong-Qi
发明人： CHOU, Ta-Te , ZHANG, Xiong-Jie , LI, Xian , FU, Hai , TIAN, Yong-Qi
IPC分类号： H01L23/28
摘要： A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.

10. 发明申请

WO2008020982A2 SEMICONDUCTOR JUNCTION DEVICE HAVING REDUCED LEAKAGE CURRENT AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有降低的泄漏电流的半导体结型器件及其形成方法
公开(公告)号：WO2008020982A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/016978
申请日：2007-07-30
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , DAI, Sheng-Huei , KING, Ya-Chin , WANG, Hai-Ning , CHIANG, Ming-Tai
发明人： DAI, Sheng-Huei , KING, Ya-Chin , WANG, Hai-Ning , CHIANG, Ming-Tai
IPC分类号： H01L21/76 , H01L29/12
CPC分类号： H01L21/76216
摘要： A semiconductor junction device includes a semiconductor substrate of a first conductivity type and a junction layer formed on the substrate which has a second conductivity type. A field reducing region of the first conductivity type surrounds a periphery of the junction layer and extends under a peripheral portion of the junction layer. An insulating layer is provided on the field reducing region and a metal layer overlies the junction layer and the insulating layer.
摘要翻译：半导体结器件包括第一导电类型的半导体衬底和形成在具有第二导电类型的衬底上的结层。第一导电类型的场减小区域围绕接合层的外围并且在接合层的外围部分下方延伸。在场减小区上提供绝缘层，金属层覆盖在接合层和绝缘层上。

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