专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004102672A1 LATERAL SOI SEMICONDUCTOR DEVICE 审中-公开
标题翻译：横向SOI半导体器件
公开(公告)号：WO2004102672A1
公开(公告)日：2004-11-25
申请号：PCT/GB2003/002025
申请日：2003-05-13
申请人： CAMBRIDGE SEMICONDUCTORS LIMITED , UDREA, Florin , GARNER, David
发明人： UDREA, Florin , GARNER, David
IPC分类号： H01L29/78
CPC分类号： H01L29/7824 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/7394 , H01L29/8086 , H01L29/861
摘要： This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.
摘要翻译：本发明通常涉及绝缘体上半导体器件，特别是对于高电压应用。描述了一种绝缘体侧向半导体器件，包括：半导体衬底; 在所述半导体衬底上的绝缘层; 和在所述绝缘体上的横向半导体器件; 所述横向半导体器件具有：第一导电类型的第一区域; 与所述第一区域横向间隔开的第二导电类型的第二区域; 以及在所述第一区域和所述第二区域之间沿横向方向延伸的漂移区域; 并且其中所述漂移区包括至少一个第一区和邻近所述第一区的至少一个第二区，具有所述第二导电类型的所述第一区，所述第二区是绝缘区，所述第一区逐渐缩窄朝向第一个地区。

2. 发明申请

WO2006123105A3 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006123105A3
公开(公告)日：2006-11-23
申请号：PCT/GB2006/001724
申请日：2006-05-11
申请人： CAMBRIDGE SEMICONDUCTOR LIMITED , UDREA, Florin
发明人： UDREA, Florin
IPC分类号： H01L29/739 , H01L21/331 , H01L29/08
摘要： A bipolar high voltage/power semiconductor device (1) has a low voltage terminal and a high voltage terminal. The device (1) has a drift region (2) of a first conductivity type and having first and second ends. In one example, a region (5) of the second conductivity type is provided at the second end of the drift region (2) connected directly to the high voltage terminal. In another example, a buffer region (6) of the first conductivity type is provided at the second end of the drift region (2) and a region (5) of the second conductivity type is provided on the other side of the buffer region (6) and connected to the high voltage terminal. Plural electrically floating island regions (9) are provided within the drift region (2) at or towards the second end of the drift region (2), the plural electrically floating island regions (9) being of the first conductivity type and being more highly doped than the drift region (2) .

3. 发明申请

WO03036699A3 LATERAL SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND CORRESPONDING MANUFACTURING METHODS 审中-公开
标题翻译：横向半导体绝缘体结构和相应的制造方法
公开(公告)号：WO03036699A3
公开(公告)日：2003-09-25
申请号：PCT/GB0204738
申请日：2002-10-21
申请人： CAMBRIDGE SEMICONDUCTOR LTD , UDREA FLORIN
发明人： UDREA FLORIN
IPC分类号： H01L21/04 , H01L21/20 , H01L21/331 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/02376 , H01L21/02378 , H01L21/02381 , H01L21/02447 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02546 , H01L21/0405 , H01L21/76251 , H01L21/84 , H01L27/1203 , H01L29/66325 , H01L29/7394
摘要： A semiconductor structure (10) has a low bandgap semiconductor layer (11), a buried insulator layer (12) below the low bandgap semiconductor layer (11), and a wide bandgap semiconductor substrate (13). The low bandgap semiconductor layer (11) may be for example silicon, SiGe, GaAs or a heterojunction. The wide bandgap semiconductor layer (13) may be for example silicon carbide or diamond. A semiconductor device may be made by bonding a wide bandgap semiconductor wafer (13) via an insulator layer (12) to a low bandgap semiconductor wafer (11) and subsequently forming a semiconductor device in the low bandgap semiconductor wafer (11).
摘要翻译：半导体结构（10）具有低带隙半导体层（11），低带隙半导体层（11）下面的掩埋绝缘体层（12）和宽带隙半导体衬底（13）。低带隙半导体层（11）可以是例如硅，SiGe，GaAs或异质结。宽带隙半导体层（13）可以是例如碳化硅或金刚石。可以通过将宽带隙半导体晶片（13）经由绝缘体层（12）接合到低带隙半导体晶片（11）并随后在低带隙半导体晶片（11）中形成半导体器件来制造半导体器件。

4. 发明申请

WO2003036699A2 LATERAL SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE 审中-公开
标题翻译：横向半导体结构及其制造方法
公开(公告)号：WO2003036699A2
公开(公告)日：2003-05-01
申请号：PCT/GB2002/004738
申请日：2002-10-21
申请人： CAMBRIDGE SEMICONDUCTOR LIMITED , UDREA, Florin
发明人： UDREA, Florin
IPC分类号： H01L21/20
CPC分类号： H01L29/7824 , H01L21/02376 , H01L21/02378 , H01L21/02381 , H01L21/02447 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02546 , H01L21/0405 , H01L21/76251 , H01L21/84 , H01L27/1203 , H01L29/66325 , H01L29/7394
摘要： A semiconductor structure (10) has a low bandgap semiconductor layer (11), a buried insulator layer (12) below the low bandgap semiconductor layer (11), and a wide bandgap semiconductor substrate (13). The low bandgap semiconductor layer (11) may be for example silicon, SiGe, GaAs or a heterojunction. The wide bandgap semiconductor layer (13) may be for example silicon carbide or diamond. A semiconductor device may be made by bonding a wide bandgap semiconductor wafer (13) via an insulator layer (12) to a low bandgap semiconductor wafer (11) and subsequently forming a semiconductor device in the low bandgap semiconductor wafer (11).
摘要翻译：半导体结构（10）具有低带隙半导体层（11），低带隙半导体层（11）下面的掩埋绝缘体层（12）和宽带隙半导体衬底（13）。低带隙半导体层（11）可以是例如硅，SiGe，GaAs或异质结。宽带隙半导体层（13）可以是例如碳化硅或金刚石。可以通过将宽带隙半导体晶片（13）经由绝缘体层（12）接合到低带隙半导体晶片（11）并随后在低带隙半导体晶片（11）中形成半导体器件来制造半导体器件。

5. 发明申请

WO2012054686A3 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 审中-公开
标题翻译： TRENCH DMOS器件具有改进的高压应用终止结构
公开(公告)号：WO2012054686A3
公开(公告)日：2012-07-05
申请号：PCT/US2011057020
申请日：2011-10-20
申请人： VISHAY GEN SEMICONDUCTOR LLC , HSU CHIH-WEI , UDREA FLORIN , LIN YIH-YIN
发明人： HSU CHIH-WEI , UDREA FLORIN , LIN YIH-YIN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/063 , H01L29/0615 , H01L29/0661 , H01L29/407 , H01L29/66143 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.
摘要翻译：功率晶体管的端接结构包括具有有源区和端接区的半导体衬底。衬底具有第一类导电性。终端沟槽位于终端区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。掺杂区域具有设置在终端沟槽下方的衬底中的第二类型的导电体。在与边界相邻的侧壁上形成MOS栅极。掺杂区域从与边界间隔开的部分MOS栅极的下方延伸到终端沟槽的远侧侧壁。端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并朝向衬底的边缘延伸。第一导电层形成在半导体衬底的背面上。第二导电层形成在有源区顶部，MOS栅极的暴露部分的顶部，并延伸以覆盖端接结构氧化物层的至少一部分。

6. 发明申请

WO2009053757A3 SHEAR STRESS SENSORS 审中-公开
标题翻译：剪应变传感器
公开(公告)号：WO2009053757A3
公开(公告)日：2009-10-15
申请号：PCT/GB2008050995
申请日：2008-10-24
申请人： CAMBRIDGE ENTPR LTD , HANEEF IBRAHEEM , HODSON HOWARD P , MILLER ROBERT , UDREA FLORIN
发明人： HANEEF IBRAHEEM , HODSON HOWARD P , MILLER ROBERT , UDREA FLORIN
IPC分类号： G01F1/684 , G01F1/708 , G01L19/00 , G01L21/10
CPC分类号： G01F1/6845 , G01F1/7084 , G01N3/24 , G01N2203/0226 , G01N2203/0623
摘要： This invention relates to hot film shear stress sensors and their fabrication. We describe a hot film shear stress sensor comprising a silicon substrate supporting a membrane having a cavity underneath, said membrane bearing a film of metal and having electrical contacts for heating said film, and wherein said membrane comprises a silicon oxide membrane, where in said metal comprises aluminium or tungsten, and wherein said membrane has a protective layer of a silicon-based material over said film of metal. In preferred embodiments the sensor is fabricated by a CMOS process and the metal comprises aluminium or tungsten.
摘要翻译：本发明涉及热膜剪切应力传感器及其制造。我们描述了一种热膜剪切应力传感器，其包括支撑具有下面空腔的膜的硅衬底，所述膜承载金属膜并具有用于加热所述膜的电触点，并且其中所述膜包括氧化硅膜，其中在所述金属包括铝或钨，并且其中所述膜在所述金属膜上具有硅基材料的保护层。在优选实施例中，传感器通过CMOS工艺制造，并且金属包括铝或钨。

7. 发明申请

WO2006024857A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：WO2006024857A1
公开(公告)日：2006-03-09
申请号：PCT/GB2005/003382
申请日：2005-09-01
申请人： CAMBRIDGE SEMICONDUCTOR LIMITED , UDREA, Florin , AMARATUNGA, Gehan, Anil, Joseph
发明人： UDREA, Florin , AMARATUNGA, Gehan, Anil, Joseph
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78 , H01L29/73 , H01L29/868 , H01L21/331
CPC分类号： H01L29/86 , H01L21/84 , H01L27/1203 , H01L29/0634 , H01L29/66325 , H01L29/7317 , H01L29/7394 , H01L29/7824 , H01L29/78603 , H01L29/868 , H02M7/003
摘要： A high voltage/power semiconductor device (100) has at least one active region (1) having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane (2) such that the active region (1) is provided at least in part over plural membranes (2). There are non-membrane regions (3) between the membranes (2). The device has a low voltage terminal (4) and a high voltage terminal (5). At least a portion of the low voltage terminal (4) and at least a portion of the high voltage terminal (5) are connected directly or indirectly to a respective one of the high voltage junctions.
摘要翻译：高电压/功率半导体器件（100）具有至少一个有效区域（1），其具有并联电连接的多个高压接点。每个高压接点的至少一部分位于相应的膜（2）中或上，使得有源区（1）至少部分地设置在多个膜（2）上。膜（2）之间有非膜区（3）。该器件具有低电压端子（4）和高压端子（5）。低电压端子（4）的至少一部分和高电压端子（5）的至少一部分直接或间接地连接到相应的一个高压接头。

8. 发明申请

WO2012054682A3 IMPROVED SCHOTTKY RECTIFIER 审中-公开
标题翻译：改进的肖特基整流器
公开(公告)号：WO2012054682A3
公开(公告)日：2012-06-21
申请号：PCT/US2011057012
申请日：2011-10-20
申请人： VISHAY GEN SEMICONDUCTOR LLC , HSU CHIH-WEI , UDREA FLORIN , LIN YIH-YIN
发明人： HSU CHIH-WEI , UDREA FLORIN , LIN YIH-YIN
IPC分类号： H01L29/872 , H01L21/329 , H01L29/868
CPC分类号： H01L29/66143 , H01L21/22 , H01L21/265 , H01L29/0619 , H01L29/872 , H01L29/8725
摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
摘要翻译：半导体整流器包括具有第一导电类型的半导体衬底。形成在衬底上的第一层具有第一类型的导电性并且比衬底更轻掺杂。具有第二类型导电性的第二层形成在衬底上，并且金属层设置在第二层上。轻掺杂第二层，使得在金属层和第二层之间形成肖特基接触。第一电极形成在金属层上方并且第二电极形成在衬底的背面上。

9. 发明申请

WO2010142342A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO2010142342A1
公开(公告)日：2010-12-16
申请号：PCT/EP2009/057261
申请日：2009-06-12
申请人： ABB RESEARCH LTD , ANTONIOU, Marina , UDREA, Florin , BAUER-HOLZER, Friedhelm
发明人： ANTONIOU, Marina , UDREA, Florin , BAUER-HOLZER, Friedhelm
IPC分类号： H01L29/739 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7395 , H01L29/0634 , H01L29/0834 , H01L29/1066 , H01L29/7392 , H01L29/7397
摘要： A power semiconductor device (1) is provided with a semiconductor wafer (10) and a first electrical contact (8) being formed on a first main side (101) of the wafer and a second electrical contact (9) being formed on a second main side (102) of the wafer opposite the first main side (101). The wafer (10) comprises a structure with a plurality of layers of different conductivity types. It comprises at least one source region (2) of the first conductivity type contacting the first electrical contact (8), at least one base region (2) of a second conductivity type contacting the first electrical contact (8), a base layer (4) and a gate electrode, which is electrically insulated by an insulation layer (51) from the source region (2) and the base region (3). The base layer (4) comprises at least one first pillar (41) of the first conductivity type and at least one second pillar (42) of the second conductivity type, the first and second pillars (41, 42) being arranged alternately in the same plane. At least one second pillar (42) is not in contact with the base region (3).
摘要翻译：功率半导体器件（1）设置有半导体晶片（10）和形成在晶片的第一主侧（101）上的第一电触点（8），第二电触点（9）形成在第二所述晶片的与所述第一主侧（101）相对的主侧（102）。晶片（10）包括具有多层不同导电类型的结构。它包括与第一电触点（8）接触的至少一个第一导电类型的源区（2），与第一电接触（8）接触的第二导电类型的至少一个基区（2），基层（ 4）和通过绝缘层（51）与源极区域（2）和基极区域（3）电绝缘的栅电极。基底层（4）包括至少一个第一导电类型的第一支柱（41）和至少一个第二导电类型的第二支柱（42），第一和第二支柱（41,42）交替布置在同一架飞机。至少一个第二柱（42）不与基部区域（3）接触。

10. 发明申请

WO2009053757A2 SHEAR STRESS SENSORS 审中-公开
标题翻译：剪切应力传感器
公开(公告)号：WO2009053757A2
公开(公告)日：2009-04-30
申请号：PCT/GB2008/050995
申请日：2008-10-24
申请人： CAMBRIDGE ENTERPRISE LIMITED , HANEEF, Ibraheem , HODSON, Howard P. , MILLER, Robert , UDREA, Florin
发明人： HANEEF, Ibraheem , HODSON, Howard P. , MILLER, Robert , UDREA, Florin
CPC分类号： G01F1/6845 , G01F1/7084 , G01N3/24 , G01N2203/0226 , G01N2203/0623
摘要： This invention relates to hot film shear stress sensors and their fabrication. We describe a hot film shear stress sensor comprising a silicon substrate supporting a membrane having a cavity underneath, said membrane bearing a film of metal and having electrical contacts for heating said film, and wherein said membrane comprises a silicon oxide membrane, where in said metal comprises aluminium or tungsten, and wherein said membrane has a protective layer of a silicon-based material over said film of metal. In preferred embodiments the sensor is fabricated by a CMOS process and the metal comprises aluminium or tungsten.
摘要翻译：本发明涉及热膜剪应力传感器及其制造。我们描述了一种热膜剪切应力传感器，其包括支撑在下面具有空腔的膜的硅基底，所述膜承载金属膜并且具有用于加热所述膜的电接触，并且其中所述膜包括氧化硅膜，其中在所述金属包括铝或钨，并且其中所述膜在所述金属膜上具有硅基材料的保护层。在优选实施例中，传感器由CMOS工艺制造，金属包括铝或钨。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式