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1. 发明申请

WO2011002612A3 CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE(E-FUSE) 审中-公开
标题翻译：用于编程和重新编程低功率，多状态电子保险丝（电子保险丝）的电路结构和方法
公开(公告)号：WO2011002612A3
公开(公告)日：2011-03-10
申请号：PCT/US2010038934
申请日：2010-06-17
申请人： IBM , ABOU-KHALIL MICHEL J , LEE TOM C , LI JUNJUN , GAUTHIER ROBERT J JR , PUTNAM CHRISTOPHER S , MITRA SOUVICK
发明人： ABOU-KHALIL MICHEL J , LEE TOM C , LI JUNJUN , GAUTHIER ROBERT J JR , PUTNAM CHRISTOPHER S , MITRA SOUVICK
IPC分类号： H01L21/82 , H01L27/02
CPC分类号： G11C17/16 , G11C11/5692 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L45/085 , H01L45/1206 , H01L45/14 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
摘要翻译：公开了电子熔丝编程/重新编程电路的实施例。在一个实施例中，电子熔丝（150）具有两个短的高原子扩散电阻导体层（110,130），其位于长的低原子扩散电阻导体（110,130）的相对侧（121,122）上和同一端（123）层（120）。使用电压源（170）来改变施加到端子（第一端= 170/161/110;第二端= 170/162/130;第三端= 170/163 / 以控制导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内电子的双向流动，从而形成开路和/或短路在长导体层 - 短导体层界面（125,126）处。这种开路和/或短路的形成可以用来实现不同的编程状态（11,01,10,00）。其他电路结构实施例将e熔丝（650）与额外的导体层和额外的端子结合，以允许更多的编程状态。还公开了相关联的电子熔丝编程和重新编程方法的实施例。

2. 发明申请

WO2008121812A1 STRUCTURE AND CIRCUIT TECHNIQUE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 审中-公开
标题翻译：具有可调触发电压的多器件半导体器件的均匀触发的结构和电路技术
公开(公告)号：WO2008121812A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/058647
申请日：2008-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel, J. , GAUTHIER, Robert , LI, Hongmei , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michel, J. , GAUTHIER, Robert , LI, Hongmei , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
IPC分类号： H02H9/00
CPC分类号： H01L27/0277 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An external current injection source (45A, 45B, 45D and 45E) is provided to individual fingers (40A-40E) of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source (45 A, 45B, 45D and 45E) is adjusted so that each finger (40A-40E) has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.
摘要翻译：外部电流注入源（45A，45B，45D和45E）被提供给多指半导体器件的单个指状物（40A-40E），以在多个手指上提供相同的触发电压。例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。调整来自每个外部电流注入源（45A，45B，45D和45E）的供给电流的大小，使得每个手指（40A-40E）具有相同的触发电压。外部电流供应电路可以包括二极管或RC触发MOSFET。可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

3. 发明申请

WO2009003151A1 SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于表征半导体器件的可选择器件选项
公开(公告)号：WO2009003151A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068452
申请日：2008-06-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHOU, Anthony, I-Chih , DUNN, James, S. , DUFRENE, Brian, M. , LUMBRA, Christopher, H. , NARASIMHA, Shreesh , PUTNAM, Christopher, S. , RAINEY, BethAnn , SCHNABEL, Christopher, M.
发明人： CHOU, Anthony, I-Chih , DUNN, James, S. , DUFRENE, Brian, M. , LUMBRA, Christopher, H. , NARASIMHA, Shreesh , PUTNAM, Christopher, S. , RAINEY, BethAnn , SCHNABEL, Christopher, M.
IPC分类号： G01R31/26 , H01L21/00
CPC分类号： G06F17/5068 , G06F2217/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system, method and program product that allows multiple devices (18) to be placed between pads (12, 14, 16) such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system (58) is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system (60) for designing a plurality of device options (dl, d2, d3, d4) for a set of chip pads (12, 14, 16); a system (62) for designing a pseudo wiring layout for each of the plurality of device options; a system (64) for selecting one of the device options; a system (66) for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system (50) for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.
摘要翻译：一种允许将多个设备（18）放置在焊盘（12,14,16）之间的系统，方法和程序产品，从而可以使用后端（BEOL）掩模改变来选择不同的设备选项。公开了一种用于实现用于表征集成电路技术中的器件的测试现场的系统（58），并且包括：用于设计用于一组芯片焊盘的多个器件选项（d1，d2，d3，d4）的系统（60）（12,14,16）; 用于为所述多个设备选项中的每一个设计伪布线布局的系统（62）用于选择所述设备选项之一的系统（64）用于将所选择的设备选项的伪布线布局映射到预定设计级的系统（66）以及用于在预定设计级别输出配置的掩模设计的系统（50），其具有为所选择的设备选项映射的布线布局。

4. 发明申请

WO2012177380A2 INTERDIGITATED VERTICAL NATIVE CAPACITOR 审中-公开
公开(公告)号：WO2012177380A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/040849
申请日：2012-06-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , THOMPSON, Eric , BOOTH, JR., Roger, A. , LU, Ning , PUTNAM, Christopher, S.
发明人： THOMPSON, Eric , BOOTH, JR., Roger, A. , LU, Ning , PUTNAM, Christopher, S.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L23/5223 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor structure includes a plurality of line level structures (15, 16, 25, 26) vertically interconnected with via level structures (31, 32, 33, 34, 41, 42). Each first line level structure (15 or 25) and each second line level structure (16 or 26) includes a set of parallel metal lines (11 or 21, 12 or 22) that is physically joined at an end to a rectangular tab structure (13 or 23, 14 or 24) having a rectangular horizontal cross-sectional area. A first set of parallel metal lines (11 or 21) within a first line level structure (15 or 25) and a second set of parallel metal lines (12 or 22) within a second line level structure (16 or 26) are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure ((11, 12) or (21, 22)). Because the rectangular tab structures (13 or 23, 14 or 24) do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures (13 or 23, 14 or 24), sub- resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure ((11, 12) or (21, 22)).
摘要翻译：金属电容器结构包括与通孔级结构（31,32,33,34,41,42）垂直相互连接的多个线路层结构（15,16,25,26）。每个第一线路层结构（15或25）和每个第二线路层结构（16或26）包括一组平行金属线（11或21,12或22），其在端部处物理地连接到矩形突起结构（ 13或23,14或24），其具有矩形水平横截面积。在第二线路层结构（16或26）内的第一线路层结构（15或25）和第二组平行金属线（12或22）内的第一组平行金属线（11或21）是交叉的，彼此平行，并且可以共同形成叉指均匀间距结构（（11,12）或（21,22））。因为矩形突片结构（13或23,14或24）在矩形突片结构（13或23,14或24）的两个相对的侧壁之间的区域内不会彼此突出，所以分解辅助特征（SRAF）可以用于在整个交叉的均匀间距结构（（11,12）或（21,22））的整个上提供均匀的宽度和均匀的间距。

5. 发明申请

WO2012047464A1 BI-DIRECTIONAL BACK-TO-BACK STACKED SCR FOR HIGH-VOLTAGE PIN ESD PROTECTION, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：用于高电压防静电保护的双向反向堆叠式SCR，制造方法和设计结构
公开(公告)号：WO2012047464A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/051500
申请日：2011-09-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel , GAUTHIER, Robert, J. , LEE, Tom, C. , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michel , GAUTHIER, Robert, J. , LEE, Tom, C. , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
IPC分类号： H01L27/04 , H01L23/60
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87 , H02H9/04
摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.
摘要翻译：提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。该器件包括对称双向背对背层叠可控硅整流器（SCR）。背对背层叠SCR（10）中的第一个的阳极（10a）连接到输入（30）。背对背层叠SCR（20）中的第二个的阳极（20a）连接到地（GND）。第一和第二背对背层叠SCR的阴极（10b，20b）连接在一起。对称双向背对背SCR中的每一个包括一对二极管（Di，D2），其将电流引向阴极，其在施加电压时变为反向偏置，从而有效地将激活元件从对称双向背对背SCR，而另一个对称双向背对背SCR的二极管（D3，D4）在与反向偏置二极管相同的方向上引导电流。

6. 发明申请

WO2011002612A2 CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE(E-FUSE) 审中-公开
标题翻译：用于编程和重新编程低功耗，多种状态，电子保险丝（电子保险丝）的电路结构和方法
公开(公告)号：WO2011002612A2
公开(公告)日：2011-01-06
申请号：PCT/US2010/038934
申请日：2010-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel, J. , LEE, Tom, C. , LI, Junjun , GAUTHIER, Robert, J., Jr. , PUTNAM, Christopher, S. , MITRA, Souvick
发明人： ABOU-KHALIL, Michel, J. , LEE, Tom, C. , LI, Junjun , GAUTHIER, Robert, J., Jr. , PUTNAM, Christopher, S. , MITRA, Souvick
IPC分类号： H01L21/82 , H01L27/02
CPC分类号： G11C17/16 , G11C11/5692 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L45/085 , H01L45/1206 , H01L45/14 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
摘要翻译：公开了电子熔丝编程/重新编程电路的实施例。在一个实施例中，电熔丝（150）具有位于长低原子扩散电阻导体的相对侧（121,122）和同一端（123）上的两个短的高原子扩散电阻导体层（110,130）层（120）。使用电压源（170）来改变极性，并且可选地改变施加到端子的电压的大小（第一端子= 170/161/110;第二端子= 170/162/130;第三端子= 170/163 / 导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内的电子的双向流动，从而形成开口和/或短路在长导体层 - 短导体层界面（125,126）处。这种打开和/或短路的形成可用于实现不同的编程状态（11，01，10，00）。其他电路结构实施例包括具有附加导体层的电子熔丝（650）和附加端子，以便允许甚至更多的编程状态。还公开了相关联的电熔丝编程和重新编程方法的实施例。

7. 发明申请

WO2005004206A3 INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS 审中-公开
标题翻译：集成电路具有平行互补鳍状件对
公开(公告)号：WO2005004206A3
公开(公告)日：2005-02-17
申请号：PCT/US2004021279
申请日：2004-06-30
申请人： IBM , BRYANT ANDRES , CLARK WILLIAM F , FRIED DAVID M , JAFFE MARK D , NOWAK EDWARD J , PEKARIK JOHN J , PUTNAM CHRISTOPHER S
发明人： BRYANT ANDRES , CLARK WILLIAM F , FRIED DAVID M , JAFFE MARK D , NOWAK EDWARD J , PEKARIK JOHN J , PUTNAM CHRISTOPHER S
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/06 , H01L21/00 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.
摘要翻译：公开了一种利用互补鳍型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片（100）的第一类型FinFET以及包括平行于第一鳍片（100）延伸的第二鳍片（102）的第二类型FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域（130）与第二类型FinFET之间的绝缘体鳍状物。绝缘体鳍状物具有与第一鳍状物（100）和第二鳍状物（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍。本发明还具有在第一类型FinFET和第二类型FinFET的沟道区上形成的共同栅极（106）。栅极（106）包括与第一类型FinFET相邻的第一杂质掺杂区域和与第二类型FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型的FinFET和第二类型的FinFET之间的差异有关的不同的功函数。第一翅片（100）和第二翅片（102）具有大致相同的宽度。

8. 发明申请

WO2005004206A2 INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS 审中-公开
标题翻译：具有并联补偿器件对的集成电路
公开(公告)号：WO2005004206A2
公开(公告)日：2005-01-13
申请号：PCT/US2004/021279
申请日：2004-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BRYANT, Andres , CLARK, William, F. , FRIED, David, M. , JAFFE, Mark, D. , NOWAK, Edward, J. , PEKARIK, John, J. , PUTNAM, Christopher, S.
发明人： BRYANT, Andres , CLARK, William, F. , FRIED, David, M. , JAFFE, Mark, D. , NOWAK, Edward, J. , PEKARIK, John, J. , PUTNAM, Christopher, S.
IPC分类号： H01L
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有第一类型的FinFET，其包括第一鳍片（100）和第二类型的FinFET，其包括平行于第一鳍片（100）延伸的第二鳍片（102）。本发明还具有位于第一第一类型的FinFET的源极/漏极区域（130）和第二类型的FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一翅片（100）和第二翅片（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间距近似等于一个鳍。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极（106）。栅极（106）包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一翅片（100）和第二翅片（102）具有大致相同的宽度。

9. 发明申请

WO2012177380A3 INTERDIGITATED VERTICAL NATIVE CAPACITOR 审中-公开
标题翻译：横向垂直电容器
公开(公告)号：WO2012177380A3
公开(公告)日：2013-02-28
申请号：PCT/US2012040849
申请日：2012-06-05
申请人： IBM , THOMPSON ERIC , BOOTH JR ROGER A , LU NING , PUTNAM CHRISTOPHER S
发明人： THOMPSON ERIC , BOOTH JR ROGER A , LU NING , PUTNAM CHRISTOPHER S
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L23/5223 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor structure includes a plurality of line level structures (15, 16, 25, 26) vertically interconnected with via level structures (31, 32, 33, 34, 41, 42). Each first line level structure (15 or 25) and each second line level structure (16 or 26) includes a set of parallel metal lines (11 or 21, 12 or 22) that is physically joined at an end to a rectangular tab structure (13 or 23, 14 or 24) having a rectangular horizontal cross-sectional area. A first set of parallel metal lines (11 or 21) within a first line level structure (15 or 25) and a second set of parallel metal lines (12 or 22) within a second line level structure (16 or 26) are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure ((11, 12) or (21, 22)). Because the rectangular tab structures (13 or 23, 14 or 24) do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures (13 or 23, 14 or 24), sub- resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure ((11, 12) or (21, 22)).
摘要翻译：金属电容器结构包括与通孔级结构（31,32,33,34,41,42）垂直互连的多个线路层结构（15,16,25,26）。每个第一线路层结构（15或25）和每个第二线路层结构（16或26）包括一组平行金属线（11或21,12或22），其在端部处物理地连接到矩形突起结构（ 13或23,14或24）具有矩形水平横截面积。在第二行级结构（16或26）内的第一行级结构（15或25）和第二组平行金属线（12或22）内的第一组平行金属线（11或21）被交叉指向，彼此平行，并且可以共同形成叉指均匀间距结构（（11,12）或（21,22））。因为矩形突片结构（13或23,14或24）在矩形突片结构（13或23,14或24）的两个相对的侧壁之间的区域内不会彼此突出，所以分解辅助特征（SRAF）可以用于在整个交叉的均匀间距结构（（11,12）或（21,22））的整个上提供均匀的宽度和均匀的间距。

10. 发明申请

WO2012102940A1 SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE 审中-公开
标题翻译：具有不对称结构的半导体绝缘体器件
公开(公告)号：WO2012102940A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/021942
申请日：2012-01-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michael, J. , GAUTHIER, Robert, J. Jr. , LEE, Tom, C. , LI, Junjun , SOUVICK, Mitra , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michael, J. , GAUTHIER, Robert, J. Jr. , LEE, Tom, C. , LI, Junjun , SOUVICK, Mitra , PUTNAM, Christopher, S.
IPC分类号： G06F17/50
CPC分类号： H01L27/0255 , G06F17/5022 , G06F17/5045 , H01L27/0262 , H01L27/1203 , H01L29/6609 , H01L29/66393 , H01L29/7436 , H01L29/861
摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode (56). The device structure includes one or more dielectric regions (20a, 20b, 20c), such as STI regions, positioned in the device region (18) and intersecting the p-n junction (52, 54) between an anode (40, 42) and cathode (28, 30, 48a, 48b, 49a, 49b, 50a, 50b). The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
摘要翻译：在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及用于横向二极管（56）的设计结构。器件结构包括位于器件区域（18）中并与pn结（52,54）相交的阳极（40,42）和阴极之间的一个或多个电介质区域（20a，20b，20c），例如STI区域（28,30,48a，48b，49a，49b，50a，50b）。可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。介质区域的宽度差和存在产生不对称二极管结构。由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

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