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1. 发明申请

WO2012047464A1 BI-DIRECTIONAL BACK-TO-BACK STACKED SCR FOR HIGH-VOLTAGE PIN ESD PROTECTION, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：用于高电压防静电保护的双向反向堆叠式SCR，制造方法和设计结构
公开(公告)号：WO2012047464A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/051500
申请日：2011-09-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel , GAUTHIER, Robert, J. , LEE, Tom, C. , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michel , GAUTHIER, Robert, J. , LEE, Tom, C. , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
IPC分类号： H01L27/04 , H01L23/60
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87 , H02H9/04
摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.
摘要翻译：提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。该器件包括对称双向背对背层叠可控硅整流器（SCR）。背对背层叠SCR（10）中的第一个的阳极（10a）连接到输入（30）。背对背层叠SCR（20）中的第二个的阳极（20a）连接到地（GND）。第一和第二背对背层叠SCR的阴极（10b，20b）连接在一起。对称双向背对背SCR中的每一个包括一对二极管（Di，D2），其将电流引向阴极，其在施加电压时变为反向偏置，从而有效地将激活元件从对称双向背对背SCR，而另一个对称双向背对背SCR的二极管（D3，D4）在与反向偏置二极管相同的方向上引导电流。

2. 发明申请

WO2011002612A2 CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE(E-FUSE) 审中-公开
标题翻译：用于编程和重新编程低功耗，多种状态，电子保险丝（电子保险丝）的电路结构和方法
公开(公告)号：WO2011002612A2
公开(公告)日：2011-01-06
申请号：PCT/US2010/038934
申请日：2010-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel, J. , LEE, Tom, C. , LI, Junjun , GAUTHIER, Robert, J., Jr. , PUTNAM, Christopher, S. , MITRA, Souvick
发明人： ABOU-KHALIL, Michel, J. , LEE, Tom, C. , LI, Junjun , GAUTHIER, Robert, J., Jr. , PUTNAM, Christopher, S. , MITRA, Souvick
IPC分类号： H01L21/82 , H01L27/02
CPC分类号： G11C17/16 , G11C11/5692 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L45/085 , H01L45/1206 , H01L45/14 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.
摘要翻译：公开了电子熔丝编程/重新编程电路的实施例。在一个实施例中，电熔丝（150）具有位于长低原子扩散电阻导体的相对侧（121,122）和同一端（123）上的两个短的高原子扩散电阻导体层（110,130）层（120）。使用电压源（170）来改变极性，并且可选地改变施加到端子的电压的大小（第一端子= 170/161/110;第二端子= 170/162/130;第三端子= 170/163 / 导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内的电子的双向流动，从而形成开口和/或短路在长导体层 - 短导体层界面（125,126）处。这种打开和/或短路的形成可用于实现不同的编程状态（11，01，10，00）。其他电路结构实施例包括具有附加导体层的电子熔丝（650）和附加端子，以便允许甚至更多的编程状态。还公开了相关联的电熔丝编程和重新编程方法的实施例。

3. 发明申请

WO2008121812A1 STRUCTURE AND CIRCUIT TECHNIQUE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 审中-公开
标题翻译：具有可调触发电压的多器件半导体器件的均匀触发的结构和电路技术
公开(公告)号：WO2008121812A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/058647
申请日：2008-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michel, J. , GAUTHIER, Robert , LI, Hongmei , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michel, J. , GAUTHIER, Robert , LI, Hongmei , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, S.
IPC分类号： H02H9/00
CPC分类号： H01L27/0277 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An external current injection source (45A, 45B, 45D and 45E) is provided to individual fingers (40A-40E) of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source (45 A, 45B, 45D and 45E) is adjusted so that each finger (40A-40E) has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.
摘要翻译：外部电流注入源（45A，45B，45D和45E）被提供给多指半导体器件的单个指状物（40A-40E），以在多个手指上提供相同的触发电压。例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。调整来自每个外部电流注入源（45A，45B，45D和45E）的供给电流的大小，使得每个手指（40A-40E）具有相同的触发电压。外部电流供应电路可以包括二极管或RC触发MOSFET。可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

4. 发明申请

WO2012102940A1 SEMICONDUCTOR-ON-INSULATOR DEVICE WITH ASYMMETRIC STRUCTURE 审中-公开
标题翻译：具有不对称结构的半导体绝缘体器件
公开(公告)号：WO2012102940A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/021942
申请日：2012-01-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michael, J. , GAUTHIER, Robert, J. Jr. , LEE, Tom, C. , LI, Junjun , SOUVICK, Mitra , PUTNAM, Christopher, S.
发明人： ABOU-KHALIL, Michael, J. , GAUTHIER, Robert, J. Jr. , LEE, Tom, C. , LI, Junjun , SOUVICK, Mitra , PUTNAM, Christopher, S.
IPC分类号： G06F17/50
CPC分类号： H01L27/0255 , G06F17/5022 , G06F17/5045 , H01L27/0262 , H01L27/1203 , H01L29/6609 , H01L29/66393 , H01L29/7436 , H01L29/861
摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode (56). The device structure includes one or more dielectric regions (20a, 20b, 20c), such as STI regions, positioned in the device region (18) and intersecting the p-n junction (52, 54) between an anode (40, 42) and cathode (28, 30, 48a, 48b, 49a, 49b, 50a, 50b). The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
摘要翻译：在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及用于横向二极管（56）的设计结构。器件结构包括位于器件区域（18）中并与pn结（52,54）相交的阳极（40,42）和阴极之间的一个或多个电介质区域（20a，20b，20c），例如STI区域（28,30,48a，48b，49a，49b，50a，50b）。可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。介质区域的宽度差和存在产生不对称二极管结构。由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

5. 发明申请

WO2008152026A2 VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE AND METHOD OF FORMING SAME 审中-公开
标题翻译：绝缘体上的垂直电流控制硅（SOI）器件及其形成方法
公开(公告)号：WO2008152026A2
公开(公告)日：2008-12-18
申请号：PCT/EP2008/057196
申请日：2008-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , GAUTHIER, JR., Robert , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, Stephen , MOUSA, Mahmoud
发明人： GAUTHIER, JR., Robert , LI, Junjun , MITRA, Souvick , PUTNAM, Christopher, Stephen , MOUSA, Mahmoud
IPC分类号： H01L27/02 , H01L29/74 , H01L21/762
CPC分类号： H01L27/0262
摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
摘要翻译：具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片和制造器件的方法（ S）。器件通过SOI表面层和绝缘体层形成在晶种孔中。通过衬底中的种子孔形成例如N型的掩埋扩散。掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。可以在掺杂的外延层上形成多晶硅，例如P型。与埋入扩散部的接触形成在接触衬里中。

6. 发明申请

WO2013055436A1 STRESS ENHANCED JUNCTION ENGINEERING FOR LATCHUP SCR 审中-公开
标题翻译：应力增强结构工程用于拉力可控制
公开(公告)号：WO2013055436A1
公开(公告)日：2013-04-18
申请号：PCT/US2012/050684
申请日：2012-08-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CAMPI, John, B. , GAUTHIER, Robert, J. , LI, Junjun , MISHRA, Rahul
发明人： CAMPI, John, B. , GAUTHIER, Robert, J. , LI, Junjun , MISHRA, Rahul
IPC分类号： H01L29/66
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A method 200 of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate 202, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area 203; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area 204; and removing the mask 205.
摘要翻译：形成包括闭锁硅可控整流器（SCR）的IC器件的方法200包括在衬底202的顶表面上形成掩模，其中掩模覆盖衬底的第一部分并暴露衬底的第二部分位于衬底上的n阱和p阱中的一个上; 蚀刻衬底的暴露的第二部分以形成蚀刻区域203; 通过在蚀刻区域204中的选择性外延沉积形成闭锁SCR的应力工程结; 并移除掩模205。

7. 发明申请

WO2010120428A2 ROBUST ESD PROTECTION CIRCUIT, METHOD AND DESIGN STRUCTURE FOR TOLERANT AND FAILSAFE DESIGNS 审中-公开
标题翻译：稳健的ESD保护电路，容错和失效设计的方法和设计结构
公开(公告)号：WO2010120428A2
公开(公告)日：2010-10-21
申请号：PCT/US2010/027774
申请日：2010-03-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CAMPI, John B. , CHANG, Shunhua T. , CHATTY, Kiran V. , GAUTHIER, Robert J. , LI, Junjun , MUHAMAD, Mujahid
发明人： CAMPI, John B. , CHANG, Shunhua T. , CHATTY, Kiran V. , GAUTHIER, Robert J. , LI, Junjun , MUHAMAD, Mujahid
IPC分类号： H01L23/60 , H01L21/336
CPC分类号： H01L27/0274 , H01L2924/0002 , H01L2924/00
摘要： A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit (200) includes a middle junction control circuit (250) that turns off a top NFET (225) of a stacked NFET electrostatic discharge (ESD) protection circuit (pad 215, ground 220, top NFET 225, bottom NFET 230, top resistor 235, and bottom resistor 240) during an ESD event.
摘要翻译：公开了用于容错和故障安全设计的强大的ESD保护电路，方法和设计结构。一个电路（200）包括一个中间结点控制电路（250），该中间结点控制电路（250）将堆叠的NFET静电放电（ESD）保护电路（焊盘215，接地220，顶部NFET 225，底部NFET 230，顶部）的顶部NFET（225）电阻器235和底部电阻器240）。

8. 发明申请

WO2012094546A1 SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
标题翻译：硅控制整流器（SCR），制造方法和设计结构
公开(公告)号：WO2012094546A1
公开(公告)日：2012-07-12
申请号：PCT/US2012/020399
申请日：2012-01-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ABOU-KHALIL, Michael, J. , CHATTY, Kiran, V. , GAUTHIER, Robert, J. , LI, Junjun
发明人： ABOU-KHALIL, Michael, J. , CHATTY, Kiran, V. , GAUTHIER, Robert, J. , LI, Junjun
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , G06F17/5045 , H01L29/0649 , H01L29/0839 , H01L29/66393 , H01L29/7436
摘要： Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well (12) on a buried insulator layer (28b) of a silicon on insulator (SOI) wafer (28). The method further includes forming a plurality of silicon controlled rectifiers (SCR) (10) in the common P-well such that N+ diffusion cathodes (20) of each of the plurality of SCRs are coupled together by the common P-well.
摘要翻译：本文公开了可控硅整流器（SCR），制造方法和设计结构。该方法包括在绝缘体上硅（SOI）晶片（28）的掩埋绝缘体层（28b）上形成公共P阱（12）。该方法还包括在公共P-阱中形成多个可控硅整流器（SCR）（10），使得多个SCR中的每一个的N +扩散阴极（20）由公共P阱耦合在一起。

9. 发明申请

WO2013148079A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 审中-公开
标题翻译： FINFET集成电路技术的被动设备
公开(公告)号：WO2013148079A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/028965
申请日：2013-03-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CLARK, William, F. , GAUTHIER, Robert, J. , LI, Junjun
IPC分类号： H01L27/108
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well (12) of a first conductivity type in a device region (22) and a doped region (52) of a second conductivity in the well. The device region is comprised of a portion of a device layer (14) of a semiconductor-on-insulator substrate (10). The doped region and a first portion of the well (57) define a junction (65). A second portion of the well (61) is positioned between the doped region (62) and an exterior sidewall (23) of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法，可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其在器件区域（22）中包括第一导电类型的阱（12）和阱中的第二导电性的掺杂区域（52）。器件区域由绝缘体上半导体衬底（10）的器件层（14）的一部分组成。掺杂区域和阱（57）的第一部分限定结（65）。阱（61）的第二部分位于装置区域的掺杂区域（62）和外侧壁（23）之间。可以对器件层的另一部分进行图案化以形成翅片型场效应晶体管的鳍片。

10. 发明申请

WO2014120450A1 ESD PROTECTION DEVICE FOR SST TRANSMITTER 审中-公开
标题翻译：用于SST发射器的ESD保护装置
公开(公告)号：WO2014120450A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/011761
申请日：2014-01-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： COX, Carrie, E. , GAUTHIER, Robert, J. , LI, Junjun , WANG, Xingle
IPC分类号： H02H9/00 , H02H3/22 , H01C7/12
CPC分类号： H02H9/046 , H01L27/0251
摘要： Aspects of the invention provide for an ESD protection device for an SST transmitter. In one embodiment, the ESD protection device includes: a primary ESD protection structure at an output of the SST transmitter; and an additional protection ESD structure in parallel with a slice of the SST transmitter, the additional ESD protection structure including: a first device in parallel with a pull-up transistor network within the slice; and a second device in parallel with a pull-down transistor network within the slice.
摘要翻译：本发明的方面提供了用于SST发射机的ESD保护装置。在一个实施例中，ESD保护装置包括：在SST发射器的输出处的主ESD保护结构; 以及与所述SST发射器的切片并联的附加保护ESD结构，所述附加ESD保护结构包括：与所述切片内的上拉晶体管网络并联的第一器件; 以及与片内的下拉晶体管网络并联的第二器件。

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