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1. 发明申请

WO2010110938A2 PULSE CONTROL FOR NONVOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：WO2010110938A2
公开(公告)日：2010-09-30
申请号：PCT/US2010/022605
申请日：2010-01-29
申请人： RAMBUS INC. , KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
发明人： KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
IPC分类号： G11C16/32 , G11C16/30 , G11C16/08
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a "rest period" between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止时间来减轻缺陷前兆的形成。第一实施例使用脉冲位线控制，其中当期望改变相关联的存储器单元中的状态时，存储器单元沟道与参考电压（响应于位线而选择）之间的耦合被脉冲化。每个脉冲可以被选择为小于大约（20）纳秒，而“休息时段” 通常选择脉冲之间的时间约为几百纳秒或更大（例如，一微秒）。由于使用了位线控制，因此可以启用非常短的上升时间，从而可以生成（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法也可以更一般地应用于其他导体（例如，用于编程或擦除操作的字线或衬底）; 如果需要的话，也可以使用分段的字线或位线，以最小化RC负载并使足够短的上升时间使脉冲稳健。

2. 发明申请

WO2009105362A1 MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES 审中-公开
标题翻译：具有可资源性的多银行闪存存储器架构
公开(公告)号：WO2009105362A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/033629
申请日：2009-02-10
申请人： RAMBUS INC. , HAUKNESS, Brent
发明人： HAUKNESS, Brent
IPC分类号： G11C16/10 , G11C16/12
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks (302), each including nonvolatile memory cells. The nonvolatile memory further includes at least one sharable resource (306), such as a power supply module, a program controller or an erase controller, wherein each sharable resource (306) is assignable to at least two of the concurrently accessible memory banks to enable a first type of memory operation. The nonvolatile memory additionally includes a number of dedicated resources (304), such as read controllers, wherein each dedicated resource (304) is configured to enable a second type of memory operation on a specific bank within the concurrently accessible memory banks.
摘要翻译：本公开描述了非易失性存储器的实施例，其包括至少两个可同时访问的存储体（302），每个包括非易失性存储单元。非易失性存储器还包括至少一个可共享资源（306），诸如电源模块，程序控制器或擦除控制器，其中每个可共享资源（306）可分配给至少两个可同时存取的存储体，以使能第一种类型的内存操作。非易失性存储器还包括多个专用资源（304），诸如读控制器，其中每个专用资源（304）被配置为使得能够在可同时存取的存储体内的特定存储体上进行第二类型的存储器操作。

3. 发明申请

WO2009064619A1 APPARATUS AND METHOD FOR SEGMENTATION OF A MEMORY DEVICE 审中-公开
标题翻译：用于分割存储器件的装置和方法
公开(公告)号：WO2009064619A1
公开(公告)日：2009-05-22
申请号：PCT/US2008/081737
申请日：2008-10-30
申请人： RAMBUS INC. , WOO, Steven C. , HAUKNESS, Brent S. , CHING, Michael T.
发明人： WOO, Steven C. , HAUKNESS, Brent S. , CHING, Michael T.
IPC分类号： G11C7/12 , G11C7/18 , G11C16/24
CPC分类号： G11C11/4097 , G11C7/18 , G11C2207/005 , G11C2207/2272
摘要： Embodiments in the present disclosure pertain to an apparatus and method for segmentation of a memory device. A bit line (100) is comprised of at least two bit line segments (102, 103) separated by a segment switch (101). When accessing memory cells (105) coupled to the bit line segment closest to the sense amplifier (104), the switch is non-conducting. Controlling the switch to be non-conducting electrically isolates the other bit line segment, thereby also electrically isolating the capacitance and resistance inherent to that bit line segment from the sense amplifier. By electrically isolating" the capacitance and resistance from the sense amplifier, self-refresh, refresh, and row activation can be performed with less power consumed and lower access latency.
摘要翻译：本公开的实施例涉及用于分割存储器件的装置和方法。位线（100）包括由段开关（101）分开的至少两个位线段（102,103）。当访问耦合到最靠近读出放大器（104）的位线段的存储单元（105）时，开关不导通。将开关控制为非导通电隔离另一个位线段，从而也将该位线段的固有电容和电阻与读出放大器电隔离。通过电隔离“感测放大器的电容和电阻，可以以较少的功耗消耗和较低的访问延迟来执行自刷新，刷新和行激活。

4. 发明申请

WO2012058324A2 RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS 审中-公开
标题翻译：电阻变化记忆体电路和方法
公开(公告)号：WO2012058324A2
公开(公告)日：2012-05-03
申请号：PCT/US2011057909
申请日：2011-10-26
申请人： RAMBUS INC , HAUKNESS BRENT
发明人： HAUKNESS BRENT
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C8/08 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0071 , G11C2013/0078 , G11C2213/79
摘要： The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
摘要翻译： 1晶体管1电阻（1T1R）型RRAM单元的存取晶体管的栅极使用电流镜相对于存取晶体管的源偏置。在施加在1T1R单元（例如通过位线）上的电压的影响下，RRAM存储元件从较高的电阻切换到较低的电阻。当RRAM存储元件从较高的电阻切换到较低的电阻时，通过RRAM单元的电流基本上由RRAM器件的较高电阻（而存取晶体管在线性区域中工作）基本确定为基本确定通过存取晶体管的饱和区工作点。

5. 发明申请

WO2011106262A3 HIERARCHICAL MEMORY ARCHITECTURE 审中-公开
标题翻译：分层存储器体系结构
公开(公告)号：WO2011106262A3
公开(公告)日：2011-12-29
申请号：PCT/US2011025487
申请日：2011-02-18
申请人： RAMBUS INC , VOGELSANG THOMAS , HAUKNESS BRENT
发明人： VOGELSANG THOMAS , HAUKNESS BRENT
IPC分类号： G11C7/12 , G11C8/08 , G11C29/00
CPC分类号： G11C11/4097 , G11C8/14 , G11C29/848 , G11C2207/002
摘要： A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column- select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.
摘要翻译：分层存储器体系结构包括一个存储器子阵列阵列，每个存储器阵列包括一个存储器单元阵列。每个子阵列由本地字线，本地列选择线和位线支持。使用主字线控制局部字线，所述主字线在平行于第一轴的方向上延伸经过多个子阵列，而局部列选择线使用在子阵列之间在垂直于第一轴。在呈现在本地字线和列选择线上的信号的方向上，每个子阵列中的位线的子集连接到主数据线，主数据线在与第二轴平行的多个子阵列上延伸。一些实施例包括基于行地址的解码而选择的冗余数据资源。

6. 发明申请

WO2009042298A1 FLASH MEMORY REFRESH 审中-公开
标题翻译：闪存记忆刷新
公开(公告)号：WO2009042298A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/072917
申请日：2008-08-12
申请人： RAMBUS INC. , HAUKNESS, Brent S. , BRONNER, Gary B.
发明人： HAUKNESS, Brent S. , BRONNER, Gary B.
IPC分类号： G11C16/34
CPC分类号： G11C16/3431 , G11C16/349
摘要： Embodiments of a circuit are described. This circuit includes storage cells having a data retention time that progressively decreases from an initial data retention time to a substantially reduced data retention time as operations are performed on at least a subset of the storage cells. Moreover, the circuit includes a refresh circuit, which is coupled to the storage cells, that refreshes data stored in one or more of the storage cells after a first refresh interval that is short enough to ensure data retention even after the data retention time of the one or more of the storage cells has decreased to the substantially reduced data retention time.
摘要翻译：描述电路的实施例。该电路包括具有从初始数据保留时间逐渐减小到基本上减少的数据保留时间的数据保留时间的存储单元，因为在存储单元的至少一个子集上执行操作。此外，电路包括与存储单元耦合的刷新电路，其刷新在第一刷新间隔之后存储在一个或多个存储单元中的数据，该第一刷新间隔足够短以确保即使在数据保留时间一个或多个存储单元已经减少到显着减少的数据保留时间。

7. 发明申请

WO2013028377A1 SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS 审中-公开
标题翻译：在RRAM电池上执行存储器操作的系统和方法
公开(公告)号：WO2013028377A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/050368
申请日：2012-08-10
申请人： RAMBUS INC. , HAUKNESS, Brent, Steven
发明人： HAUKNESS, Brent, Steven
IPC分类号： G11C13/00 , G11C16/06
CPC分类号： G11C13/0026 , G11C13/0002 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/79
摘要： A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
摘要翻译：电阻RAM（RRAM）器件具有位线，字线，承载基本静态和非负电压的偏置电压的源极线，RRAM单元和耦合到位线电路的位线控制。 RRAM单元包括耦合到字线的栅极节点，耦合到源极线的偏置节点和耦合到位线的位线节点。位线控制电路被配置为产生非负指令电压，以对RRAM单元执行相应的存储器操作。

8. 发明申请

WO2011106054A1 MULTILEVEL DRAM 审中-公开
标题翻译：多媒体DRAM
公开(公告)号：WO2011106054A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058533
申请日：2010-12-01
申请人： RAMBUS INC. , KOYA, Yoshihito , HAUKNESS, Brent
发明人： KOYA, Yoshihito , HAUKNESS, Brent
IPC分类号： G11C11/4074 , G11C11/4094 , G11C11/4091
CPC分类号： G11C7/16 , G11C11/401 , G11C11/4091 , G11C11/4097 , G11C11/565 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2207/005 , G11C2207/2254
摘要： A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.
摘要翻译：多级动态随机存取存储器（MLDRAM）使用存储在单个存储器单元中的单元电压来表示多于一位的原始位组合。电池电压是多个离散的模拟电压范围之一，每个离散模拟电压范围分别对应于位组合的可能值的相应一个。在读取选定的存储单元时，存储的电荷通过本地位线传送到前置放大器。前置放大器放大本地位线上的信号，并用表示存储电压的模拟信号驱动全局位线。数字转换器将全局位线上的模拟信号转换为读位组合。读取位组合然后通过全局位线移动到数据高速缓存。数据高速缓存将模拟电压写入存储单元以写入新值或恢复在读取单元格时销毁的数据。

9. 发明申请

WO2010123681A2 PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE 审中-公开
标题翻译：存储器控制器和存储器件之间的刷新协议
公开(公告)号：WO2010123681A2
公开(公告)日：2010-10-28
申请号：PCT/US2010/030166
申请日：2010-04-07
申请人： RAMBUS INC. , WARE, Frederick A. , HAUKNESS, Brent
发明人： WARE, Frederick A. , HAUKNESS, Brent
IPC分类号： G11C11/401 , G11C11/402 , G11C11/403
CPC分类号： G11C11/40611 , G06F13/1636 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C2211/4067 , Y02D10/14
摘要： The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.
摘要翻译：本实施例提供一种支持存储设备中的自刷新操作的系统。在操作期间，系统将存储器设备从自动刷新状态转变，其中存储器控制器将存储器设备的刷新操作控制到自刷新状态，其中存储器设备控制刷新操作。当存储器件处于自刷新状态时，系统将刷新操作的进程信息从存储器件发送到存储器控制器。接下来，当从自刷新状态返回到自动刷新状态时，系统使用从存储装置接收到的进度信息来控制存储器控制器的后续操作的顺序。

10. 发明申请

WO2010090691A3 MULTIPLE PLANE, NON-VOLATILE MEMORY WITH SYNCHRONIZED CONTROL 审中-公开
标题翻译：具有同步控制的多平面，非易失性存储器
公开(公告)号：WO2010090691A3
公开(公告)日：2010-09-30
申请号：PCT/US2009069504
申请日：2009-12-23
申请人： RAMBUS INC , HAUKNESS BRENT STEVEN
发明人： HAUKNESS BRENT STEVEN
IPC分类号： G06F12/02 , G06F9/06 , G06F12/08 , G06F13/16
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10 , G11C16/32 , G11C16/3454 , G11C2216/22 , G11C2216/24
摘要： This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the "program phase" and the "verify phase" of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
摘要翻译：本公开提供了一种多平面闪存设备，其中高电压编程（设置）或擦除（重置）脉冲被定时为同时发生。通过调节每个存储平面（例如，具有其自己的专用阵列控制和页缓冲器的存储器的每个逻辑或物理分区）何时施加高电压脉冲，可以减少控制多个并发操作所需的开销电路，从而节省宝贵的管芯空间。每个状态改变操作周期的“程序阶段”和“验证阶段”都可以一次跨所有平面进行编排，共享时序和高电压分布。

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