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1. 发明申请

WO2009064619A1 APPARATUS AND METHOD FOR SEGMENTATION OF A MEMORY DEVICE 审中-公开
标题翻译：用于分割存储器件的装置和方法
公开(公告)号：WO2009064619A1
公开(公告)日：2009-05-22
申请号：PCT/US2008/081737
申请日：2008-10-30
申请人： RAMBUS INC. , WOO, Steven C. , HAUKNESS, Brent S. , CHING, Michael T.
发明人： WOO, Steven C. , HAUKNESS, Brent S. , CHING, Michael T.
IPC分类号： G11C7/12 , G11C7/18 , G11C16/24
CPC分类号： G11C11/4097 , G11C7/18 , G11C2207/005 , G11C2207/2272
摘要： Embodiments in the present disclosure pertain to an apparatus and method for segmentation of a memory device. A bit line (100) is comprised of at least two bit line segments (102, 103) separated by a segment switch (101). When accessing memory cells (105) coupled to the bit line segment closest to the sense amplifier (104), the switch is non-conducting. Controlling the switch to be non-conducting electrically isolates the other bit line segment, thereby also electrically isolating the capacitance and resistance inherent to that bit line segment from the sense amplifier. By electrically isolating" the capacitance and resistance from the sense amplifier, self-refresh, refresh, and row activation can be performed with less power consumed and lower access latency.
摘要翻译：本公开的实施例涉及用于分割存储器件的装置和方法。位线（100）包括由段开关（101）分开的至少两个位线段（102,103）。当访问耦合到最靠近读出放大器（104）的位线段的存储单元（105）时，开关不导通。将开关控制为非导通电隔离另一个位线段，从而也将该位线段的固有电容和电阻与读出放大器电隔离。通过电隔离“感测放大器的电容和电阻，可以以较少的功耗消耗和较低的访问延迟来执行自刷新，刷新和行激活。

2. 发明申请

WO2009042298A1 FLASH MEMORY REFRESH 审中-公开
标题翻译：闪存记忆刷新
公开(公告)号：WO2009042298A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/072917
申请日：2008-08-12
申请人： RAMBUS INC. , HAUKNESS, Brent S. , BRONNER, Gary B.
发明人： HAUKNESS, Brent S. , BRONNER, Gary B.
IPC分类号： G11C16/34
CPC分类号： G11C16/3431 , G11C16/349
摘要： Embodiments of a circuit are described. This circuit includes storage cells having a data retention time that progressively decreases from an initial data retention time to a substantially reduced data retention time as operations are performed on at least a subset of the storage cells. Moreover, the circuit includes a refresh circuit, which is coupled to the storage cells, that refreshes data stored in one or more of the storage cells after a first refresh interval that is short enough to ensure data retention even after the data retention time of the one or more of the storage cells has decreased to the substantially reduced data retention time.
摘要翻译：描述电路的实施例。该电路包括具有从初始数据保留时间逐渐减小到基本上减少的数据保留时间的数据保留时间的存储单元，因为在存储单元的至少一个子集上执行操作。此外，电路包括与存储单元耦合的刷新电路，其刷新在第一刷新间隔之后存储在一个或多个存储单元中的数据，该第一刷新间隔足够短以确保即使在数据保留时间一个或多个存储单元已经减少到显着减少的数据保留时间。

3. 发明申请

WO2015084971A1 REDUCED CURRENT MEMORY DEVICE 审中-公开
标题翻译：减少电流存储器件
公开(公告)号：WO2015084971A1
公开(公告)日：2015-06-11
申请号：PCT/US2014/068394
申请日：2014-12-03
申请人： RAMBUS INC. , SEKAR, Deepak Chandra , HAUKNESS, Brent S. , BATEMAN, Bruce L.
发明人： SEKAR, Deepak Chandra , HAUKNESS, Brent S. , BATEMAN, Bruce L.
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C13/003 , G11C13/0097 , H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.
摘要翻译：存储器件包括分别耦合到多个存储器单元的本地位线和通过分别具有第一和第二阻抗的第一和第二可选择并行路径的全局位线。第一路径在设置操作或形成操作中的至少一个中有效，并且第二路径在复位操作中有效。选择存储器元件的选择器件包括具有第一掺杂级别的漏极和具有低于第一掺杂级别的第二掺杂级的源极，其中该器件被配置为向电阻器提供第一导通阻抗或第二阻抗存储元件响应于控制信号。

4. 发明申请

WO2008067494A1 INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION 审中-公开
标题翻译：具有内置加热电路的集成电路反向运行变化
公开(公告)号：WO2008067494A1
公开(公告)日：2008-06-05
申请号：PCT/US2007/085979
申请日：2007-11-29
申请人： RAMBUS INC. , BRONNER, Gary , HAUKNESS, Brent S. , ASSADERAGHI, Fariborz , KELLAM, Mark D. , HOROWITZ, Mark
发明人： BRONNER, Gary , HAUKNESS, Brent S. , ASSADERAGHI, Fariborz , KELLAM, Mark D. , HOROWITZ, Mark
IPC分类号： H01L23/34 , H01L21/8247 , H01L27/105 , H05B3/14 , H01L21/00
CPC分类号： H01L27/105 , H01L21/67103 , H01L23/345 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).
摘要翻译：集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。存储器件的字线或位线用作加热元件（107）。

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