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1. 发明申请

WO2010110938A3 PULSE CONTROL FOR NONVOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：WO2010110938A3
公开(公告)日：2010-11-11
申请号：PCT/US2010022605
申请日：2010-01-29
申请人： RAMBUS INC , KELLAM MARK D , HAUKNESS BRENT STEVEN , BRONNER GARY B , DONNELLY KEVIN
发明人： KELLAM MARK D , HAUKNESS BRENT STEVEN , BRONNER GARY B , DONNELLY KEVIN
IPC分类号： G11C16/32 , G11C16/08 , G11C16/30
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a "rest period" between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当需要改变相关联的存储器单元中的状态时，存储器单元通道与参考电压（响应于位线选择）之间的耦合是脉冲式的。每个脉冲可以选择为小于约（20）纳秒，而脉冲之间的“休止期”通常被选择为约百纳秒或更大（例如，一微秒）的数量级。由于使用位线控制，所以可以启用非常短的上升时间，能够产生（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 如果需要，还可以使用分段字线或位线来最小化RC负载并且使足够短的上升时间使得脉冲变得坚固。

2. 发明申请

WO2010083006A2 METHODS AND CIRCUITS FOR DETECTING AND REPORTING HIGH-ENERGY PARTICLES USING MOBILE PHONES AND OTHER PORTABLE COMPUTING DEVICES 审中-公开
标题翻译：使用移动电话和其他便携式计算设备检测和报告高能粒子的方法和电路
公开(公告)号：WO2010083006A2
公开(公告)日：2010-07-22
申请号：PCT/US2009/068802
申请日：2009-12-18
申请人： RAMBUS INC. , BEST, Scott , BRONNER, Gary , TSERN, Ely
发明人： BEST, Scott , BRONNER, Gary , TSERN, Ely
IPC分类号： H04W88/02 , H04W24/10 , H04W64/00
CPC分类号： H04W36/385 , G01T7/00 , H04M2250/12
摘要： Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone- specific error data can serve as user-specific dosimeters.
摘要翻译：描述了结合使用通常可用的半导体存储器形成的辐射探测器的移动电话。辐射探测器只需要很少或不需要额外的硬件，而不需要额外的硬件，因此可以用很少的费用或封装修改进行集成。低成本支持广泛的探测器分布。从配备探测器的移动电话星座收集的数据可用于定位遗失或被盗的核材料或其他潜在危险的辐射源。电话用户可以在其周围发出辐射危险警报，综合电话特定的错误数据可以用作用户特定的剂量计。

3. 发明申请

WO2009094298A1 MULTI-PAGE PARALLEL PROGRAM FLASH MEMORY 审中-公开
标题翻译：多页并行程序闪存
公开(公告)号：WO2009094298A1
公开(公告)日：2009-07-30
申请号：PCT/US2009/031191
申请日：2009-01-16
申请人： RAMBUS INC. , KOYA, Yoshihito , BRONNER, Gary , WARE, Frederick, A.
发明人： KOYA, Yoshihito , BRONNER, Gary , WARE, Frederick, A.
IPC分类号： G11C16/10 , G11C16/04 , G11C16/24
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/24
摘要： A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.
摘要翻译：具有位线和与其耦合的多个存储单元的NAND快闪存储器件。编程电路同时耦合到多个存储单元，以对与相同位线相关联的不同NAND串中的两个或更多个存储单元进行编程。

4. 发明申请

WO2008067494A1 INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION 审中-公开
标题翻译：具有内置加热电路的集成电路反向运行变化
公开(公告)号：WO2008067494A1
公开(公告)日：2008-06-05
申请号：PCT/US2007/085979
申请日：2007-11-29
申请人： RAMBUS INC. , BRONNER, Gary , HAUKNESS, Brent S. , ASSADERAGHI, Fariborz , KELLAM, Mark D. , HOROWITZ, Mark
发明人： BRONNER, Gary , HAUKNESS, Brent S. , ASSADERAGHI, Fariborz , KELLAM, Mark D. , HOROWITZ, Mark
IPC分类号： H01L23/34 , H01L21/8247 , H01L27/105 , H05B3/14 , H01L21/00
CPC分类号： H01L27/105 , H01L21/67103 , H01L23/345 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).
摘要翻译：集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。存储器件的字线或位线用作加热元件（107）。

5. 发明申请

WO2012178114A3 RESISTANCE MEMORY CELL 审中-公开
标题翻译：电阻存储单元
公开(公告)号：WO2012178114A3
公开(公告)日：2013-04-11
申请号：PCT/US2012043884
申请日：2012-06-22
申请人： RAMBUS INC , KELLAM MARK D , BRONNER GARY B
发明人： KELLAM MARK D , BRONNER GARY B
IPC分类号： G11C13/00 , G11C7/10 , G11C7/20
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0083 , G11C2213/72 , H01L27/2409 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143
摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low- resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
摘要翻译：电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。双端子存取装置影响电阻存储单元的电流 - 电压特性。电阻存储器还包括一个电路，在电阻存储单元两端施加具有设定极性的设定脉冲，将电阻存储单元设置为在施加设定脉冲后保持的低电阻状态，具有复位极性的复位脉冲与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态的电阻存储单元，而不改变电阻存储单元的电阻状态。

6. 发明申请

WO2011068694A2 DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE 审中-公开
标题翻译： DRAM感应放大器，支持低存储单元电容
公开(公告)号：WO2011068694A2
公开(公告)日：2011-06-09
申请号：PCT/US2010057362
申请日：2010-11-19
申请人： RAMBUS INC , VOGELSANG THOMAS , BRONNER GARY B
发明人： VOGELSANG THOMAS , BRONNER GARY B
IPC分类号： G11C11/4091 , G11C11/407 , G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/08 , G11C11/4094 , G11C11/4096 , H01L27/10873 , H01L27/10897
摘要： The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold- voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.
摘要翻译：所公开的实施例提供用于动态随机存取存储器（DRAM）的读出放大器。该读出放大器包括将被耦合到要在DRAM中感测的单元的位线以及在位线上传送信号的补充的补充位线。读出放大器还包括包括交叉耦合的PFET的p型场效应晶体管（PFET）对，其选择性地将位线或补位线耦合到高位线电压。读出放大器还包括包括交叉耦合的NFET的n型场效应晶体管（NFET）对，其选择性地将位线或补位线接地。该NFET对被轻掺杂以在NFET对中的NFET之间提供低阈值电压失配。在一个变型中，用于NFET的栅极材料被选择为具有补偿由轻基板掺杂导致的NFET中的负阈值电压的功函数。在另一变型中，读出放大器还包括交叉耦合的一对锁存NFET。这些锁存NFET通常被掺杂并且被配置为在轻掺杂NFET完成感测位线上的电压之后锁存位线上的电压。

7. 发明申请

WO2010083006A3 METHODS AND CIRCUITS FOR DETECTING AND REPORTING HIGH-ENERGY PARTICLES USING MOBILE PHONES AND OTHER PORTABLE COMPUTING DEVICES 审中-公开
标题翻译：检测和报告使用移动电话和其他便携式计算设备的高能粒子的方法和电路
公开(公告)号：WO2010083006A3
公开(公告)日：2010-10-21
申请号：PCT/US2009068802
申请日：2009-12-18
申请人： RAMBUS INC , BEST SCOTT , BRONNER GARY , TSERN ELY
发明人： BEST SCOTT , BRONNER GARY , TSERN ELY
IPC分类号： H04W88/02 , H04W24/10 , H04W64/00
CPC分类号： H04W36/385 , G01T7/00 , H04M2250/12
摘要： Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone- specific error data can serve as user-specific dosimeters.
摘要翻译：描述的是携带使用常用半导体存储器形成的辐射探测器的移动电话。辐射探测器对常规电话中可用的几乎没有额外的硬件，因此可以以少量的费用或包装修改来集成。低成本支持检测器的广泛分布。从装有探测器的手机的星座收集的数据可用于定位错误或被盗的核材料或其他潜在危险的辐射源。电话用户可以收到附近的辐射危险警报，并且聚合的手机特定的错误数据可以用作用户特定的剂量计。

8. 发明申请

WO2009042298A1 FLASH MEMORY REFRESH 审中-公开
标题翻译：闪存记忆刷新
公开(公告)号：WO2009042298A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/072917
申请日：2008-08-12
申请人： RAMBUS INC. , HAUKNESS, Brent S. , BRONNER, Gary B.
发明人： HAUKNESS, Brent S. , BRONNER, Gary B.
IPC分类号： G11C16/34
CPC分类号： G11C16/3431 , G11C16/349
摘要： Embodiments of a circuit are described. This circuit includes storage cells having a data retention time that progressively decreases from an initial data retention time to a substantially reduced data retention time as operations are performed on at least a subset of the storage cells. Moreover, the circuit includes a refresh circuit, which is coupled to the storage cells, that refreshes data stored in one or more of the storage cells after a first refresh interval that is short enough to ensure data retention even after the data retention time of the one or more of the storage cells has decreased to the substantially reduced data retention time.
摘要翻译：描述电路的实施例。该电路包括具有从初始数据保留时间逐渐减小到基本上减少的数据保留时间的数据保留时间的存储单元，因为在存储单元的至少一个子集上执行操作。此外，电路包括与存储单元耦合的刷新电路，其刷新在第一刷新间隔之后存储在一个或多个存储单元中的数据，该第一刷新间隔足够短以确保即使在数据保留时间一个或多个存储单元已经减少到显着减少的数据保留时间。

9. 发明申请

WO2013028376A2 RESISTIVE RAM DEVICE HAVING IMPROVED SWITCHING CHARACTERISTICS 审中-公开
标题翻译：具有改进的开关特性的电阻RAM设备
公开(公告)号：WO2013028376A2
公开(公告)日：2013-02-28
申请号：PCT/US2012/050363
申请日：2012-08-10
申请人： RAMBUS INC. , KELLAM, Mark, D. , BRONNER, Gary, B.
发明人： KELLAM, Mark, D. , BRONNER, Gary, B.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/085 , G11C13/0011 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A resistive RAM device, comprising a first electrode, a second electrode, an electrolyte layer located between the first electrode and the second electrode. The first electrode has a central region surrounded by a peripheral region in a plane parallel to the electrolyte layer, and the first electrode comprises a protrusion extending into the electrolyte layer by a greater extent in the central region than in the peripheral region so that the electrolyte layer is thinner in the central region than in the peripheral region.
摘要翻译：一种电阻RAM装置，包括第一电极，第二电极，位于第一电极和第二电极之间的电解质层。第一电极具有由与电解质层平行的平面中的周边区域围绕的中心区域，第一电极包括在中心区域比在周边区域中更大程度地延伸到电解质层中的突起，使得电解质中心区域的层比外围区域薄。

10. 发明申请

WO2012178114A2 RESISTANCE MEMORY CELL 审中-公开
标题翻译：电阻存储单元
公开(公告)号：WO2012178114A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/043884
申请日：2012-06-22
申请人： RAMBUS INC. , KELLAM, Mark, D. , BRONNER, Gary, B.
发明人： KELLAM, Mark, D. , BRONNER, Gary, B.
IPC分类号： G11C13/00 , G11C7/10 , G11C7/20
CPC分类号： G11C13/004 , G11C13/00 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0073 , G11C2013/0083 , G11C2213/72 , H01L27/2409 , H01L27/2418 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143
摘要： A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low- resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.
摘要翻译：电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。双端子存取装置影响电阻存储单元的电流 - 电压特性。电阻存储器还包括一个电路，在电阻存储单元两端施加具有设定极性的设定脉冲，将电阻存储单元设置为在施加设定脉冲后保持的低电阻状态，具有复位极性的复位脉冲与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态的电阻存储单元，而不改变电阻存储单元的电阻状态。

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