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1. 发明申请

WO2014081982A1 CAPACITOR USING MIDDLE OF LINE (MOL) CONDUCTIVE LAYERS 审中-公开
标题翻译：电容器使用中线（MOL）导电层
公开(公告)号：WO2014081982A1
公开(公告)日：2014-05-30
申请号：PCT/US2013/071347
申请日：2013-11-21
申请人： QUALCOMM INCORPORATED
发明人： CHIDAMBARAM, PR , YANG, Bin
IPC分类号： H01L49/02 , H01L23/522 , H01L27/06
CPC分类号： H01L27/0629 , H01L23/5223 , H01L23/5228 , H01L28/20 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate (330) of the MIM capacitor as well as a first set of local interconnects (120-1...4) to source and drain regions (104, 106) of a semiconductor device. The method also includes depositing an insulator layer (340) on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer (350) on the insulator layer as a second plate of the MIM capacitor.
摘要翻译：一种用于制造金属 - 绝缘体 - 金属（MIM）电容的方法，包括在半导体衬底的浅沟槽隔离（STI）区域上沉积第一中间线（MOL）导电层。第一MOL导电层提供MIM电容器的第一板（330）以及到半导体器件的源区和漏区（104,106）的第一组局部互连（120-1 ... 4）。该方法还包括在第一MOL导电层上沉积作为MIM电容器的电介质层的绝缘体层（340）。该方法还包括在MIM电容器的第二板上沉积在绝缘体层上的第二MOL导电层（350）。

2. 发明申请

WO2014062705A1 MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR 审中-公开
标题翻译：基于磁性隧道结的随机数发生器
公开(公告)号：WO2014062705A1
公开(公告)日：2014-04-24
申请号：PCT/US2013/065091
申请日：2013-10-15
申请人： QUALCOMM INCORPORATED
发明人： LEE, Kangho , KIM, Taehyun , ZHU, Xiaochun , JACOBSON, David M. , MADALA, Raghu Sagar , WU, Wenqing , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset.
摘要翻译：示出了利用由STT-MTJ熵控制器控制的磁隧道结（MTJ）的随机数发生器系统，其通过监测基于MTJ的随机数发生器的健康来确定是否继续生成随机数。如果随机数生成的健康状况高于阈值，则STT-MTJ熵控制器关闭基于MTJ的随机数生成器，并且向请求芯片组发送消息，即不可能产生安全密钥。如果随机数生成的健康状况低于阈值，则熵控制器允许基于MTJ的随机数发生器基于指定的算法产生随机数，其输出被后处理并由加密质量确定性随机使用以产生请求芯片组的安全密钥。

3. 发明申请

WO2014043574A2 REFERENCE CELL REPAIR SCHEME 审中-公开
标题翻译：参考细胞修复方案
公开(公告)号：WO2014043574A2
公开(公告)日：2014-03-20
申请号：PCT/US2013/059808
申请日：2013-09-13
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul
IPC分类号： G11C29/00
CPC分类号： G11C11/16 , G11C11/165 , G11C11/1673 , G11C29/787 , G11C29/832
摘要： In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node.
摘要翻译：在磁随机存取存储器（MRAM）中，参考位单元的多个阵列通过将它们各自的位线耦合到合并的参考节点而耦合在一起。耦合在相应的参考位线和合并的参考节点之间的通过门电路被配置用于选择性地将一个或多个参考位线耦合或去耦合到合并的参考节点。传递门电路通过编程耦合到通路电路的一次可编程器件来控制。一次性可编程器件可以被编程为将参考位单元的有缺陷的阵列与合并的参考节点去耦合，或者在用于耦合到参考节点的参考位单元的冗余阵列之间进行选择。

4. 发明申请

WO2014039573A1 MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR 审中-公开
标题翻译：基于磁性隧道结的随机数发生器
公开(公告)号：WO2014039573A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058083
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： ZHU, Xiaochu , WU, Wenqing , JACOBSON, David M. , KANG, Seung H. , YUEN, Kendrick H.
IPC分类号： G06F7/58
CPC分类号： G06F7/582 , G06F7/588
摘要： Embodiments of the disclosure are directed to generating a random number. An embodiment of the disclosure passes a current (210; 510; 610; 1010) from a read operation (202; 502; 602; 1002) through a magnetic tunnel junction (MTJ) (200; 500; 600; 700a; 700b; 1000) to cause a first magnetization orientation of a free layer (204; 504; 604; 704; 1004) to switch to a second magnetization orientation, the switch in magnetization orientation causing a change in a resistance of the MTJ, and periodically samples the resistance of the MTJ to generate a bit value for the random number.
摘要翻译：本公开的实施例涉及生成随机数。本公开的一个实施例将来自读取操作（202; 502; 602; 1002）的电流（210; 510; 610; 1010）通过磁性隧道结（MTJ）（200; 500; 600; 700a; 700b; 1000 ）引起自由层（204; 504; 604; 704; 1004）的第一磁化取向切换到第二磁化取向，磁化方向上的开关引起MTJ的电阻的变化，并周期性地对电阻进行采样的MTJ来生成随机数的位值。

5. 发明申请

WO2014039565A1 LOW COST PROGRAMMABLE MULTI-STATE DEVICE 审中-公开
标题翻译：低成本可编程多状态器件
公开(公告)号：WO2014039565A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058075
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , KANG, Seung H.
IPC分类号： H01L23/525 , H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： G11C17/02 , G11C11/005 , G11C11/5607 , G11C11/5692 , G11C17/00 , G11C17/14 , G11C17/16 , G11C17/165 , H01L23/5252 , H01L23/5256 , H01L27/22 , H01L27/224 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a preprogrammed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metalinsulator- metal (MIM) capacitor structure.
摘要翻译：仅使用一个，两个或三个掩模，在后端（BEOL）过程中构造了一次性可编程（OPT）和多时间可编程（MTP）结构。 OTP / MTP结构可以编程为三种状态之一，预编程高电阻状态，可编程低电阻状态和可编程非常高电阻状态。在可编程低电阻状态下，在抗熔丝编程期间阻挡层被分解，使得OTP / MTP结构呈现出百欧姆量级的电阻。在非常高的电阻状态下，在编程期间导通熔丝被断开，使得OTP / MTP结构呈现以兆欧姆数量级的电阻。 OTP / MTP结构可以包括磁隧道结（MTJ）结构或金属绝缘体金属（MIM）电容器结构。

6. 发明申请

WO2014039558A1 FINFET CAPACITOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： FINFET电容器及其制造方法
公开(公告)号：WO2014039558A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058066
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： ZHANG, Ron , CHUA-EOAN, Lew G. , GU, Shiqun
IPC分类号： H01L21/84 , H01L27/06 , H01L27/12 , H01L27/13 , H01L49/02
CPC分类号： H01L27/0629 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L27/13 , H01L28/86 , H01L29/66795
摘要： Capacitors are disclosed that can be manufactured in a FinFET- compatible process. The capacitors comprise fins (506, 508) formed on a substrate, wherein the fins are separated from each by a capacitor dielectric material. The fins having the same polarity are connected to each other by means of cap connections (510, 512).
摘要翻译：公开了可以以与FinFET兼容的工艺制造的电容器。电容器包括形成在基板上的散热片（506,508），其中散热片通过电容器电介质材料与每个分离。具有相同极性的翅片通过盖连接（510,512）彼此连接。

7. 发明申请

WO2013169780A1 CIRCUITS CONFIGURED TO REMAIN IN A NON-PROGRAM STATE DURING A POWER-DOWN EVENT 审中-公开
标题翻译：在下电事件期间配置为非程序状态的电路
公开(公告)号：WO2013169780A1
公开(公告)日：2013-11-14
申请号：PCT/US2013/039952
申请日：2013-05-07
申请人： QUALCOMM INCORPORATED
发明人： TERZIOGLU, Esin , UVIEGHARA, Gregory, A. , SANI, Mehdi, H. , KOTA, Anil , YOON, Sei, Seung
IPC分类号： G11C7/24 , G11C17/16 , G11C17/18
CPC分类号： G11C7/24 , G11C17/16 , G11C17/18
摘要： [0071] In a particular embodiment, an apparatus includes a one- time programmable (OTP) memory circuit (324) configured to be responsive to a programming voltage (308). The OTP memory circuit includes an OTP memory array (220) including OTP memory cells, a first power switch (326) configured to decouple the OTP memory array (220) from the programming voltage (308), and a second power switch (328) configured to decouple a subset of the OTP memory cells from the programming voltage (308). Control logic (216) controls the power switches (326, 328) and is configured to maintain the OTP memory array (220) in a non-program state during a power-down event
摘要翻译：在特定实施例中，装置包括被配置为响应于编程电压（308）的一次可编程（OTP）存储器电路（324）。 OTP存储器电路包括包括OTP存储器单元的OTP存储器阵列（220），被配置为将OTP存储器阵列（220）与编程电压（308）去耦的第一电源开关（326）和第二电源开关（328）被配置为将OTP存储器单元的子集与编程电压（308）分离。控制逻辑（216）控制功率开关（326,328），并且被配置为在断电事件期间将OTP存储器阵列（220）维持在非程序状态

8. 发明申请

WO2013138467A1 POWER GATING FOR HIGH SPEED XBAR ARCHITECTURE 审中-公开
标题翻译：用于高速XBAR架构的功率增益
公开(公告)号：WO2013138467A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/030884
申请日：2013-03-13
申请人： QUALCOMM INCORPORATED
发明人： RAO, Hari M. , TERZIOGLU, Esin , BOYNAPALLI, Venugopal
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , Y02D10/151
摘要： A low power interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce energy consumption and delay. Repeaters inserted into XBAR data paths reduce resistance capacitance (RC) delays so that a design can support desired frequency specifications along a path. Dynamic power consumption is reduced by inserting latch repeaters in the XBAR track. The latch repeaters each include a transmission gate and a latch. Select circuitry couples selected clients to a path. Enable circuitry opens the transmission gates located on the path between the selected clients. Latch repeaters that are not enabled on a given communication cycle gate off the unused portions of the path and maintain the data that was latched on a previous cycle.
摘要翻译：低功耗互连允许客户端使用XBAR架构进行客户端通信。 XBAR编译器生成具有XBAR数据路径的芯片设计，以减少能耗和延迟。插入XBAR数据路径的中继器可以减少电阻（RC）延迟，从而使设计能够沿着路径支持所需的频率规格。通过在XBAR轨道中插入锁存中继器来降低动态功耗。锁存中继器各自包括传输门和锁存器。选择电路将选定的客户端耦合到路径。启用电路打开位于所选客户端之间路径上的传输门。在给定通信周期中未启用的锁存中继器将关闭路径的未使用部分，并维护在先前周期中锁存的数据。

9. 发明申请

WO2013130423A1 MEMORY PRE-DECODER CIRCUITS EMPLOYING PULSE LATCH(ES) FOR REDUCING MEMORY ACCESS TIMES, AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：使用脉冲锁存器（ES）减少存储器访问时间的内存预解码器电路及相关系统和方法
公开(公告)号：WO2013130423A1
公开(公告)日：2013-09-06
申请号：PCT/US2013/027723
申请日：2013-02-26
申请人： QUALCOMM INCORPORATED
发明人： TERZIOGLU, Esin , JUNG, Changho , NAZAR, Shahzad
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a predecoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.
摘要翻译：公开了采用用于减少存储器访问时间的脉冲锁存器的存储器预解码器电路以及相关的系统和方法。在一个实施例中，存储器预解码器电路包括存储器预解码器，其被配置为对在存储器预解码设置路径内输入的存储器地址进行预解码，以生成预解码存储器地址输入。此外，在存储器预解码设置路径外部的存储器预解码器电路中提供脉冲锁存器。脉冲锁存器基于时钟信号对预解码的存储器地址输入进行采样，并产生预解码的存储器地址输出。这样，存储器预译码设置路径在脉冲锁存器的时钟信号之前设置预先解码的存储器地址输入。以这种方式，脉冲锁存器被配置为产生预解码的存储器地址输出，而不增加存储器预解码设置路径中的建立时间。

10. 发明申请

WO2013112946A1 MULTI-LANE HIGH-SPEED INTERFACES FOR HIGH SPEED SYNCHRONOUS SERIAL INTERFACE (HSI), AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：用于高速同步串行接口（HSI）的多LAN高速接口及相关系统和方法
公开(公告)号：WO2013112946A1
公开(公告)日：2013-08-01
申请号：PCT/US2013/023308
申请日：2013-01-25
申请人： QUALCOMM INCORPORATED
发明人： SHACHAM, Assaf , GIL, Amit
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： Multi-lane high speed interfaces for a modified High Speed Synchronous Serial (HSI) system, and related systems methods are disclosed. In one embodiment, electronic device using a modified HSI protocol comprises a transmit communications interface. The transmit communications interface comprises a data path configured to carry data from the electronic device, a ready path configured to carry an HSI protocol compliant READY signal, and a flag path configured to carry an HSI protocol compliant FLAG signal indicative of repeated bit values of data carried on the data path. The transmit communications interface further comprises one or more additional data paths configured to carry additional data from the electronic device in parallel with the data carried by the data path such that the data path and the one or more additional data paths carry HSI protocol compliant data striped across the data path and the one or more additional data paths.
摘要翻译：公开了用于修改的高速同步串行（HSI）系统的多通道高速接口以及相关的系统方法。在一个实施例中，使用修改的HSI协议的电子设备包括发射通信接口。发射通信接口包括被配置为携带来自电子设备的数据的数据路径，被配置为携带符合HSI协议的READY信号的准备路径，以及被配置为携带指示重复的数据位值的符合HSI协议的FLAG信号的标志路径承载数据路径。发射通信接口还包括一个或多个附加数据路径，其被配置为与数据路径携带的数据并行地携带来自电子设备的附加数据，使得数据路径和一个或多个附加数据路径携带符合HSI协议的数据条带跨数据路径和一个或多个附加数据路径。

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