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1. 发明申请

WO2012160863A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2012160863A1
公开(公告)日：2012-11-29
申请号：PCT/JP2012/056788
申请日：2012-03-09
申请人： KABUSHIKI KAISHA TOSHIBA , DEGUCHI, Jun , TODA, Haruki
发明人： DEGUCHI, Jun , TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C2013/0073 , G11C2013/0085 , G11C2013/0088 , G11C2013/009 , G11C2213/71 , G11C2213/77
摘要： A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括设置在多个第一线和多条第二线的交点处的多个存储单元; 和写电路。写入电路在执行写入操作时执行第一步骤，跨连接到数据写入目标的选择的存储器单元的第一和第二线路施加电压，并跨越连接到第一和第二线路的不同电压所述多个存储单元的数据写未指定的未选择的存储单元，并且在执行所述第一步骤之后，执行第二步骤，在连接到所选存储单元的第一和第二行上施加数据写入所需的电压并且将连接到未选择的存储单元的第一和第二线中的至少一个引入浮动状态。

2. 发明申请

WO2009113699A1 INFORMATION RECORDING DEVICE AND INFORMATION RECORDING/REPRODUCTION SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：信息记录装置和包括其的信息记录/再现系统
公开(公告)号：WO2009113699A1
公开(公告)日：2009-09-17
申请号：PCT/JP2009/054978
申请日：2009-03-10
申请人： KABUSHIKI KAISHA TOSHIBA , ARAKI, Takeshi , TSUKAMOTO, Takayuki , YAMAGUCHI, Takeshi
发明人： ARAKI, Takeshi , TSUKAMOTO, Takayuki , YAMAGUCHI, Takeshi
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： This disclosure provides an information recording device for use in a non-volatile information recording/reproduction system having a high recording density, the device including a resistive material having less phase separation or the like during switching. This disclosure also provides an information recording/reproduction system including the device. This disclosure provides an information recording device including: a pair of electrodes; and a recording layer between the electrodes, the recording layer recording information by its resistance change, the recording layer including at least one of (a) M 3 O z and (b) A x M 3 _ x 0 z as a main component, in (a) and (b), z being a value representing oxygen deficiency from z = 4.5, and in (b), x satisfying 0.00
摘要翻译：本公开提供了一种用于具有高记录密度的非易失性信息记录/再现系统中的信息记录装置，该装置包括在切换期间具有较小相位分离等的电阻材料。本公开还提供了包括该设备的信息记录/再现系统。本公开提供一种信息记录装置，包括：一对电极; （a）和（b）中的（a）M3Oz和（b）AxM3_x0z中的至少一个作为主要成分，记录层通过其电阻变化记录信息，记录层记录信息，z 是从z = 4.5表示氧缺乏的值，在（b）中，x满足0.00

3. 发明申请

WO2009038220A1 RESISTANCE-CHANGING MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：WO2009038220A1
公开(公告)日：2009-03-26
申请号：PCT/JP2008/067362
申请日：2008-09-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆可设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

4. 发明申请

WO2010035609A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：WO2010035609A1
公开(公告)日：2010-04-01
申请号：PCT/JP2009/065139
申请日：2009-08-25
申请人： KABUSHIKI KAISHA TOSHIBA , ITAGAKI, Kiyotaro , IWATA, Yoshihisa , TANAKA, Hiroyasu , KIDOH, Masaru , KATSUMATA, Ryota , KITO, Masaru , AOCHI, Hideaki , NITAYAMA, Akihiro
发明人： ITAGAKI, Kiyotaro , IWATA, Yoshihisa , TANAKA, Hiroyasu , KIDOH, Masaru , KATSUMATA, Ryota , KITO, Masaru , AOCHI, Hideaki , NITAYAMA, Akihiro
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

5. 发明申请

WO2009051274A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2009051274A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/069285
申请日：2008-10-17
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , KUBO, Koichi , FUKUDA, Yasuyuki
发明人： NAGASHIMA, Hiroyuki , KUBO, Koichi , FUKUDA, Yasuyuki
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/3413 , G11C16/3463 , G11C2013/0073 , G11C2013/0092 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器产生用于根据写入数据改变可变电阻器的电阻的多种类型的写入脉冲。选择电路将由脉冲发生器产生的写脉冲施加到存储单元。读出放大器对存储单元执行验证读取。状态判定电路根据读出放大器的输出决定验证结果。控制电路基于来自状态判定电路的验证结果对存储器单元执行附加写入。

6. 发明申请

WO2008099723A1 SEMICONDUCTOR MEMORY WITH REED- SOLOMON DECODER 审中-公开
标题翻译：具有REED SOLOMON解码器的半导体存储器
公开(公告)号：WO2008099723A1
公开(公告)日：2008-08-21
申请号：PCT/JP2008/051903
申请日：2008-01-30
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1575 , G06F11/1068 , H03M13/1515
摘要： A semiconductor memory device such as a flash memory with a memory cell array and a double-error correcting Reed-Solomon decoder, comprising: means for transforming the error location polynomial through variable transformation in order to obtain a unique coefficient depending on the syndromes; a lookup table for determining the error locations from the unique coefficient; and means for determining said unique coefficient from the syndromes through computation in a Residue Number System in order to achieve parallel processing and to reduce the quantity of computations, for example using residues through 15 and 17 when processing in GF (256)
摘要翻译：具有存储单元阵列和双误差校正里德 - 所罗门解码器的半导体存储器件，例如闪存，包括：用于通过变量变换来变换错误位置多项式以便获得独特系数取决于综合征; 一个用于从唯一系数确定错误位置的查找表; 以及用于通过残差数系统中的计算从所述综合征确定所述唯一系数以便实现并行处理并且减少计算量的装置，例如当在GF（256）中处理时使用残差15和17，

7. 发明申请

WO2012147446A1 DATA RECORDING DEVICE, HOST DEVICE AND METHOD OF PROCESSING DATA RECORDING DEVICE 审中-公开
标题翻译：数据记录装置，主机装置和处理数据记录装置的方法
公开(公告)号：WO2012147446A1
公开(公告)日：2012-11-01
申请号：PCT/JP2012/058282
申请日：2012-03-22
申请人： KABUSHIKI KAISHA TOSHIBA , KATO, Taku , NAGAI, Yuji , MATSUSHITA, Tatsuyuki
发明人： KATO, Taku , NAGAI, Yuji , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , G06F21/20 , G06F21/24 , H04L9/32
CPC分类号： H04L9/0869 , G06F21/10 , G06F21/445 , G06F21/73 , G06F21/78 , G06F2221/0724 , H04L9/0861 , H04L9/0866 , H04L9/3263 , H04L2209/60
摘要： A controller is provided with a controller key and a first controller identification information unique to the controller. The controller generates a controller unique key unique to a respective controller based on the controller key and the first controller identification information, and a second controller identification information based on the first controller identification information. A decryptor decrypts the encrypted medium device key using the controller unique key to obtain a medium device key. An authentication/key exchange process unit performs authentication/key exchange process with the host device through an interface unit using the medium device key and the medium device key certificate to establish the secure channel.
摘要翻译：控制器具有控制器键和控制器独有的第一控制器识别信息。所述控制器基于所述控制器键和所述第一控制器识别信息生成对于相应控制器特有的控制器唯一密钥，以及基于所述第一控制器标识信息的第二控制器识别信息。解密器使用控制器唯一密钥对加密的介质设备密钥进行解密以获得中等设备密钥。认证/密钥交换处理单元通过使用介质设备密钥和介质设备密钥证书的接口单元与主机设备进行认证/密钥交换处理，以建立安全信道。

8. 发明申请

WO2012147445A1 DATA RECORDING DEVICE, AND METHOD OF PROCESSING DATA RECORDING DEVICE 审中-公开
标题翻译：数据记录装置，以及处理数据记录装置的方法
公开(公告)号：WO2012147445A1
公开(公告)日：2012-11-01
申请号：PCT/JP2012/058281
申请日：2012-03-22
申请人： KABUSHIKI KAISHA TOSHIBA , KATO, Taku , NAGAI, Yuji , MATSUSHITA, Tatsuyuki
发明人： KATO, Taku , NAGAI, Yuji , MATSUSHITA, Tatsuyuki
IPC分类号： H04L9/08 , G06F21/20 , G06F21/24 , H04L9/32
CPC分类号： H04L63/061 , G06F21/44 , G06F21/445 , G06F21/72 , G06F21/73 , G06F21/78 , G06F21/85 , H04L9/0844 , H04L9/0866 , H04L9/0869 , H04L9/3247 , H04L9/3263 , H04L2209/60
摘要： A controller is provided with a controller key and a first controller identification information unique to the controller. The controller generates a controller unique key unique to a respective controller based on the controller key and the first controller identification information, and a second controller identification information based on the first controller identification information. A decryptor decrypts the encrypted medium device key using the controller unique key to obtain a medium device key. An authentication/key exchange process unit performs authentication/key exchange process with the host device through an interface unit using the medium device key, the medium device key certificate and the second controller identification information to establish a secure channel.
摘要翻译：控制器具有控制器键和控制器独有的第一控制器识别信息。所述控制器基于所述控制器键和所述第一控制器识别信息生成对于相应控制器特有的控制器唯一密钥，以及基于所述第一控制器标识信息的第二控制器识别信息。解密器使用控制器唯一密钥对加密的介质设备密钥进行解密以获得中等设备密钥。认证/密钥交换处理单元通过使用介质设备密钥，介质设备密钥证书和第二控制器标识信息的接口单元与主机设备进行认证/密钥交换处理，以建立安全信道。

9. 发明申请

WO2010018715A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2010018715A1
公开(公告)日：2010-02-18
申请号：PCT/JP2009/062019
申请日：2009-06-24
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , INOUE, Hirofumi
发明人： NAGASHIMA, Hiroyuki , INOUE, Hirofumi
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
摘要翻译：一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括多个第一线，与该多条第一线相交的多个第二线，以及多个存储单元，被布置成矩阵并连接在两条线之间的第一和第二线的交点处每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路，其操作以同时访问在单元阵列中彼此物理分离的存储单元。

10. 发明申请

WO2009075370A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：WO2009075370A1
公开(公告)日：2009-06-18
申请号：PCT/JP2008/072727
申请日：2008-12-09
申请人： KABUSHIKI KAISHA TOSHIBA , FUKUZUMI, Yoshiaki , KATSUMATA, Ryota , KIDOH, Masaru , KITO, Masaru , TANAKA, Hiroyasu , KOMORI, Yosuke , ISHIDUKI, Megumi , AOCHI, Hideaki
发明人： FUKUZUMI, Yoshiaki , KATSUMATA, Ryota , KIDOH, Masaru , KITO, Masaru , TANAKA, Hiroyasu , KOMORI, Yosuke , ISHIDUKI, Megumi , AOCHI, Hideaki
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers eachhaving a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells.
摘要翻译：非挥发性半导体存储装置具有多个存储串，其中多个电可重写存储单元串联连接。每个存储串包括第一半导体层，每个半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分和形成为耦合该对柱状部分的下端的耦合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分和电荷存储层的侧表面的第一导电层。第一导电层用作存储器单元的栅电极。

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