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1. 发明申请

WO2015085977A1 METHOD FOR READING A RESISTIVE MEMORY CELL, AND A MEMORY CELL FOR IMPLEMENTATION 审中-公开
标题翻译：方法用于读取电阻式存储单元和细胞为了便于实施
公开(公告)号：WO2015085977A1
公开(公告)日：2015-06-18
申请号：PCT/DE2014000551
申请日：2014-10-29
申请人： FORSCHUNGSZENTRUM JÜLICH GMBH , RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE
发明人： RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE , VAN DEN HURK JAN , LINN EIKE , WASER RAINER , VALOV ILIA
IPC分类号： F16H48/40
CPC分类号： G11C13/004 , G11C13/0011 , G11C13/0069 , G11C2013/0047 , G11C2013/0052 , G11C2213/33 , G11C2213/52 , H01L45/08 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/148
摘要： The invention has involved the development of a method for reading a resistive memory cell that has two electrodes spaced apart from one another by an ion-conductive resistive material and that can be transferred from a stable state having a relatively high resistance value (high resistive state, HRS) to a stable state having a relatively low resistance value (low resistance state, LRS) by applying a write voltage. According to the invention, reading involves a read voltage being applied as a read pulse, wherein the number of ions driven through the ion-conductive resistive material during the pulse is set by means of the level and duration of the pulse such that, on the basis of the state for forming an electrically conductive path through the ion-conductive resistive material, they suffice at least until the onset of a flow of current through this path and hence for the transition to a metastable state VRS (volatile resistance state) with a reduced resistance value and a prescribed relaxation time for the return to the HRS state, but not for the transition to the LRS state. This ensures that the memory cell is always back in the same state after reading as before reading. This renders particularly memory elements that consist of two memory cells in reverse-connected series being nondestructively readable without this diminishing the possibility of producing large arrays from these memory elements.
摘要翻译：在本发明，用于读取具有两个电阻式存储器单元的方法，通过离子导电电阻材料的电极，其特征在于通过施加稳定状态的写入电压具有较高的电阻值（高电阻状态，HRS）间隔开的是具有较低电阻值的稳定状态（低电阻状态，LRS）可变换显影。根据本发明，将读取电压施加读脉冲，用于读出，其特征在于，设置的通过的数量和脉冲的持续时间的离子导电电阻材料的离子在脉冲期间被驱动的数量，以便开始从状态电阻以形成通过离子传导的导电路径材料至少直到电流流过该路径，从而过渡到亚稳态的充分降低电阻值和预定的松弛时间为返回到状态HRS，但不为到状态LRS过渡发作（VRS挥发性电阻状态），通过这种方式，确保了读出后的存储器单元肯定是早在相同的条件读数前。这使得特定存储器元件，其包括两个存储器单元的反串联连接的非破坏性读出而不这降低了实现这些存储元件的大阵列的可能性。

2. 发明申请

WO2014045512A1 不揮発性記憶装置およびその制御方法审中-公开
标题翻译：非易失存储器件及其控制方法
公开(公告)号：WO2014045512A1
公开(公告)日：2014-03-27
申请号：PCT/JP2013/004823
申请日：2013-08-09
申请人：学校法人中央大学
发明人：岩崎　友こ , 宮地　幸祐 , 竹内　健
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C29/06 , G11C2013/0047 , G11C2013/0057 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , G11C2213/82
摘要：　抵抗記憶素子にディスターブが発生することを防ぎつつ、読み出し速度や書き込み速度を向上させる。　本発明に係る不揮発性記憶装置１００は、不揮発性の抵抗記憶素子を少なくとも１つ備えるメモリ１０２と、抵抗記憶素子に高抵抗状態または低抵抗状態を書き込む制御部１０４とを備え、制御部１０４は、高抵抗状態の書き込み後の検証動作時に抵抗記憶素子に印加するバイアスの方向と、低抵抗状態の書き込み後の検証動作時に抵抗記憶素子に印加するバイアスの方向とを逆方向とする。
摘要翻译：本发明的目的是提高读取速率和写入速率，同时防止电阻存储元件中的干扰的发生。根据本发明的非易失性存储装置（100）包括具有至少一个非易失性电阻存储元件的存储器（102）和用于将高电阻状态或低电阻状态写入电阻存储元件的控制单元（104）。控制单元（104）在写入高电阻状态之后的验证操作期间反转施加到电阻存储元件的偏压的方向，以及在写入低电阻之后的验证操作期间施加到电阻存储元件的偏置的方向州。

3. 发明申请

WO2009098169A1 ORALLY DISINTEGRATING TABLETS WITH SPECKLED APPEARANCE 审中-公开
标题翻译：用特别的外观进行ORALLY DISCAMATING TABLETS
公开(公告)号：WO2009098169A1
公开(公告)日：2009-08-13
申请号：PCT/EP2009/051055
申请日：2009-01-30
申请人： ALPEX PHARMA SA , STROPPOLO, Federico , ARDALAN, Shahbaz
发明人： STROPPOLO, Federico , ARDALAN, Shahbaz
IPC分类号： A61K9/26 , A61K47/26 , A61K31/137 , A61K31/5415
CPC分类号： A61K9/2072 , A61K9/2077 , A61K31/137 , A61K31/5415 , A61K47/26 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/3431 , G11C16/349 , G11C2013/0047 , G11C2013/0052
摘要： Orally disintegrating tablets containing colored granules of a water-soluble sugar which give them a speckled appearance are described. The orally disintegrating tablets with speckled appearance are readily and easy identifiable by physicians, nurses and patients.
摘要翻译：描述含有赋予它们斑点外观的水溶性糖的着色颗粒的口腔崩解片剂。具有斑点外观的口腔崩解片剂由医生，护士和患者容易识别。

4. 发明申请

WO2010136056A1 RESISTIVE STORAGE CELL, CROSSBAR ARRAY CIRCUIT, RESISTIVE RANDOM ACCESS MEMORY DEVICE AND READ-OUT-METHOD 审中-公开
标题翻译：电阻存储单元，跨桥阵列电路，电阻随机存取存储器和读出方法
公开(公告)号：WO2010136056A1
公开(公告)日：2010-12-02
申请号：PCT/EP2009/006015
申请日：2009-08-19
申请人： RHEINISCH-WETFÄLISCHE TECHNISCHE HOCHSCHULE AACHEN , FORSCHUNGSZENTRUM JÜLICH , LINN, Eike , WASER, Rainer , ROSEZIN, Roland , KÜGELER, Carsten
发明人： LINN, Eike , WASER, Rainer , ROSEZIN, Roland , KÜGELER, Carsten
IPC分类号： G11C13/00 , G11C13/02 , G11C11/56
CPC分类号： G11C13/004 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2013/0047 , G11C2213/15 , G11C2213/71 , G11C2213/77
摘要： The invention relates to a resistive storage cell. According to the invention said resistive storage cell is a passive resistive storage cell (22) comprising a pair of two at least functionally identical resistive switching storage members (34, 36), said two resistive switching storage members (34, 36) are connected in series in a serial connection path (32) and are electrically anti-parallel orientated within the serial connection path (32). The invention further relates to a corresponding crossbar array circuit (12) comprising a plurality of said resistive storage cells (22), a corresponding resistive random access memory device (10) and a method for reading out information from a bipolar resistive storage cell.
摘要翻译：本发明涉及电阻式存储单元。根据本发明，所述电阻存储单元是包括一对至少两个至少功能相同的电阻式开关存储构件（34,36）的无源电阻存储单元（22），所述两个电阻式开关存储构件（34,36）连接在串联连接路径（32）并且在串联连接路径（32）内电反平行取向。本发明还涉及包括多个所述电阻存储单元（22），相应的电阻随机存取存储器件（10）和从双极性电阻存储单元读出信息的方法的相应交叉开关阵列电路（12）。

5. 发明申请

WO2009038220A1 RESISTANCE-CHANGING MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：WO2009038220A1
公开(公告)日：2009-03-26
申请号：PCT/JP2008/067362
申请日：2008-09-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆可设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

6. 发明申请

WO2008048597A2 CROSSBAR-MEMORY SYSTEMS AND METHODS FOR WRITING TO AND READING FROM CROSSBAR MEMORY JUNCTIONS OF CROSSBAR-MEMORY SYSTEMS 审中-公开
标题翻译：交叉记忆体系统和用于写入和读取跨轨存储器系统的跨轨存储器连接的方法
公开(公告)号：WO2008048597A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/022070
申请日：2007-10-16
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L. P. , ROBINETT, Warren , KUEKES, Philip, J.
发明人： ROBINETT, Warren , KUEKES, Philip, J.
IPC分类号： G11C13/02
CPC分类号： G11C13/02 , B82Y10/00 , G06F11/1008 , G06F11/1076 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/009 , G11C2213/16 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system (1300) comprises a first layer of microscale signal lines (808), a second layer of microscale signal lines (810), a first layer of nanowires (804) configured so that each first layer nanowire overlaps each first layer microscale signal line (808), and a second layer of nanowires (806) configured so that each second layer nanowire overlaps each second layer microscale signal line (810) and overlaps each first layer nanowire (804). The crossbar-memory system includes nonlinear-tunneling resistors (1526,1528) configured to selectively connect first layer nanowires (804) to first layer microscale signal lines (808) and to selectively connect second layer nanowires (806) to second layer microscale signal lines (810). The crossbar-memory system (1300) also includes nonlinear tunneling-hysteretic resistors (1318) configured to connect each first layer nanowire (2008) to each second layer nanowire (2012) at each crossbar intersection.
摘要翻译：本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。在本发明的一个实施例中，交叉开关存储器系统（1300）包括第一层微米级信号线（808），第二层微型信号线（810），第一层纳米线（804），其构造成使得每个第一层纳米线与每个第一层微米信号线（808）重叠，并且第二纳米线层（806）被配置为使得每个第二层纳米线与每个第二层微米信号线（810）重叠并与每个第一层纳米线（804）重叠，。交叉开关存储器系统包括非线性隧道电阻器（1526,1528），其被配置为选择性地将第一层纳米线（804）连接到第一层微米信号线（808），并且将第二层纳米线（806）选择性地连接到第二层微米信号线（810）。交叉开关存储器系统（1300）还包括非线性隧道迟滞电阻器（1318），其被配置为在每个交叉点交叉处将每个第一层纳米线（2008）连接到每个第二层纳米线（2012）。

7. 发明申请

WO2016160146A1 INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB 审中-公开
标题翻译：集成的SETBACK读取与减少的反应障碍
公开(公告)号：WO2016160146A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/017870
申请日：2016-02-12
申请人： INTEL CORPORATION
发明人： KRIPANIDHI, Arjun , PANGAL, Kiran , LEEM, Lark-Hoon , SRINIVASAN, Balaji
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0047 , G11C2013/0052 , G11C2013/0066
摘要： Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed
摘要翻译：本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测的挫折脉冲，PCM单元是处于非晶态还是结晶状态。可以描述和/或要求保护其他实施例

8. 发明申请

WO2015138281A1 MITIGATING READ DISTURB IN A CROSS-POINT MEMORY 审中-公开
标题翻译：减少跨点记忆中的读取干扰
公开(公告)号：WO2015138281A1
公开(公告)日：2015-09-17
申请号：PCT/US2015/019366
申请日：2015-03-09
申请人： INTEL CORPORATION , CHU, Daniel J. , PANGAL, Kiran , FRANKLIN, Nathan R. , DAMLE, Prashant S. , CHAOHONG, Hu
发明人： CHU, Daniel J. , PANGAL, Kiran , FRANKLIN, Nathan R. , DAMLE, Prashant S. , CHAOHONG, Hu
IPC分类号： G11C13/00 , G11C7/06 , G11C7/10
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C2013/0047 , G11C2013/0052
摘要： The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
摘要翻译：本公开涉及减轻交叉点存储器中的读取干扰。设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控制器。存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。

9. 发明申请

WO2008048597A3 CROSSBAR-MEMORY SYSTEMS WITH NANOWIRE CROSSBAR JUNCTIONS 审中-公开
标题翻译：具有NANOWIRE CROSSBAR JUNCTIONS的交叉记忆体系统
公开(公告)号：WO2008048597A3
公开(公告)日：2008-06-19
申请号：PCT/US2007022070
申请日：2007-10-16
申请人： HEWLETT PACKARD DEVELOPMENT CO , ROBINETT WARREN , KUEKES PHILIP J
发明人： ROBINETT WARREN , KUEKES PHILIP J
IPC分类号： G11C13/02
CPC分类号： G11C13/02 , B82Y10/00 , G06F11/1008 , G06F11/1076 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/009 , G11C2213/16 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system (800) comprises a first layer of microscale signal lines (808), a second layer of microscale signal lines '(810), a first layer of nanowires (804) configured so that each first layer, nanowire overlaps each first layer microscale signal line (808), and a second layer of nanowires (806) configured so that each second layer nanowire overlaps each second layer microscale signal line (810) and overlaps each first layer nanowire (804). The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires (804) to first layer microscale signal lines (808) and to selectively connect second layer nanowires (806) to second layer microscale signal lines (810). The crossbar-memory system (800) also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire. at each crossbar intersection.
摘要翻译：本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。在本发明的一个实施例中，交叉开关存储器系统（800）包括第一层微米信号线（808），第二层微米信号线（810），第一层纳米线（804）每个第一层纳米线与每个第一层微米信号线（808）重叠，以及第二纳米线层（806），其被配置为使得每个第二层纳米线与每个第二层微米信号线（810）重叠并与每个第一层纳米线 804）。交叉开关存储器系统包括被配置为选择性地将第一层纳米线（804）连接到第一层微型信号线（808）并且选择性地将第二层纳米线（806）连接到第二层微量信号线（810）的非线性隧道电阻器。交叉开关存储器系统（800）还包括被配置为将每个第一层纳米线连接到每个第二层纳米线的非线性隧道 - 迟滞电阻器。在每个交叉口交叉点。

10. 发明申请

WO2005073976A1 MOLECULAR MEMORY DEVICES AND METHODS 审中-公开
标题翻译：分子存储器件和方法
公开(公告)号：WO2005073976A1
公开(公告)日：2005-08-11
申请号：PCT/US2005/003133
申请日：2005-01-28
申请人： ZETTACORE, INC. , KUHR, Werner, G. , GALLO, Antonio, R.
发明人： KUHR, Werner, G. , GALLO, Antonio, R.
IPC分类号： G11C13/02
CPC分类号： G11C13/0069 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/009 , G11C2213/15 , G11C2213/71 , G11C2213/79 , H01L27/285 , H01L51/0077 , H01L51/0595
摘要： A molecular memory element comprising a switching device; at least a first bit line and a first word line coupled to said switching device; and an array of storage locations, each coupled to a bit line and a word line, said elements comprising a first electrode with storage molecules comprising redox active molecules, and said array comprising a second electrode.
摘要翻译：一种分子存储元件，包括开关装置; 至少第一位线和耦合到所述开关器件的第一字线; 以及存储位置阵列，每个存储位置分别耦合到位线和字线，所述元件包括具有包含氧化还原活性分子的存储分子的第一电极，所述阵列包括第二电极。

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