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1. 发明申请

WO2010018715A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2010018715A1
公开(公告)日：2010-02-18
申请号：PCT/JP2009/062019
申请日：2009-06-24
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , INOUE, Hirofumi
发明人： NAGASHIMA, Hiroyuki , INOUE, Hirofumi
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
摘要翻译：一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括多个第一线，与该多条第一线相交的多个第二线，以及多个存储单元，被布置成矩阵并连接在两条线之间的第一和第二线的交点处每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路，其操作以同时访问在单元阵列中彼此物理分离的存储单元。

2. 发明申请

WO2009051276A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：WO2009051276A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/069287
申请日：2008-10-17
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , NAKAI, Hiroto
发明人： NAGASHIMA, Hiroyuki , NAKAI, Hiroto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F12/0246 , G06F12/0893 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C16/3431 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.
摘要翻译：信息处理系统包括可操作地存储数据的主存储器和可操作以访问主存储器以用于数据的控制电路。主存储器包括：非易失性半导体存储器件，其包含电可擦除的可编程非易失性存储单元，每个可擦除可编程非易失性存储单元使用可变电阻器;以及DRAM，其布置在控制电路和非易失性半导体存储器件非易失性半导体存储器件具有重写存储数据的刷新模式。控制电路基于对非易失性半导体存储器件的访问次数，在所述刷新模式下激活非易失性半导体存储器件。

3. 发明申请

WO2009050969A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2009050969A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/066613
申请日：2008-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
发明人： NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0004 , G11C13/0009 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

4. 发明申请

WO2005031751A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH USES SOME MEMORY BLOCKS IN MULTILEVEL MEMORY AS BINARY MEMORY BLOCKS 审中-公开
标题翻译：非易失性半导体存储器件，其在多个存储器中使用一些存储块作为二进制存储器块
公开(公告)号：WO2005031751A1
公开(公告)日：2005-04-07
申请号：PCT/JP2004/012420
申请日：2004-08-23
申请人： KABUSHIKI KAISHA TOSHIBA , SanDisk Corporation , NAGASHIMA, Hiroyuki , TANAKA, Tomoharu , KAWAI, Koichi , QUADER, Khandker, N.
发明人： NAGASHIMA, Hiroyuki , TANAKA, Tomoharu , KAWAI, Koichi , QUADER, Khandker, N.
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/10 , G11C2211/5641
摘要： A nonvolatile semiconductor memory device includes a memory cell array, interface, and write circuit. The write circuit can selectively write data in the memory cell array by first write procedures or second write procedures in accordance with a data write command input to the interface. When a data write command by the first write procedures is input from the interface, the write circuit executes the command when flag data has a first value and does not execute the command when the flag data has a second value.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，接口和写入电路。写入电路可以根据输入到接口的数据写入命令，通过第一写入过程或第二写入过程来选择性地将数据写入存储单元阵列。当从接口输入通过第一写入过程的数据写入命令时，当标志数据具有第一值时，写入电路执行命令，并且当标志数据具有第二值时不执行命令。

5. 发明申请

WO2009096136A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2009096136A1
公开(公告)日：2009-08-06
申请号：PCT/JP2008/073905
申请日：2008-12-22
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki
发明人： NAGASHIMA, Hiroyuki
IPC分类号： G11C29/00
CPC分类号： G11C29/883 , G11C29/76 , G11C29/82 , G11C29/88
摘要： There is provided a semiconductor memory device having a plurality of memory cell layers which can be used even if part of the memory cell layers is determined as defective. The semiconductor memory device includes a stacked memory cell array having a laminated plurality of memory cell layers, each of which has a plurality of blocks; a layer quality information storing circuit (10) which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify a memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and address converting circuit (11) in which if an externally input address input from outside corresponds to the block in the defective memory cell layer, the externally input address is address-converted so as to correspond to the block of the normal memory cell layer.
摘要翻译：提供了具有多个存储单元层的半导体存储器件，即使存储单元层的一部分被确定为有缺陷，也可以使用该存储单元层。半导体存储器件包括层叠的存储单元阵列，其具有层叠的多个存储单元层，每个存储单元层具有多个块; 层质量信息存储电路（10），其可以存储表示各个存储单元层是正常存储单元层还是缺陷存储单元层的层质量信息，以识别发现有缺陷块的数量的存储单元层等于或大于预定数量作为缺陷存储单元层，而其它存储单元层作为正常存储单元层; 以及地址转换电路（11），其中如果从外部输入的外部输入地址对应于缺陷存储单元层中的块，则将外部输入的地址进行地址转换，以对应于正常存储单元层的块。

6. 发明申请

WO2009051274A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2009051274A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/069285
申请日：2008-10-17
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , KUBO, Koichi , FUKUDA, Yasuyuki
发明人： NAGASHIMA, Hiroyuki , KUBO, Koichi , FUKUDA, Yasuyuki
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/3413 , G11C16/3463 , G11C2013/0073 , G11C2013/0092 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器产生用于根据写入数据改变可变电阻器的电阻的多种类型的写入脉冲。选择电路将由脉冲发生器产生的写脉冲施加到存储单元。读出放大器对存储单元执行验证读取。状态判定电路根据读出放大器的输出决定验证结果。控制电路基于来自状态判定电路的验证结果对存储器单元执行附加写入。

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