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41. 发明申请

WO2018044368A1 STATE-DEPENDENT READ COMPENSATION 审中-公开
标题翻译：与状态相关的读取补偿
公开(公告)号：WO2018044368A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/033300
申请日：2017-05-18
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHOU, Zhenming , LIANG, Guirong , HEMINK, Gerrit Jan , LEE, Dana , GORLA, Chandu , PUTHENTHERMADAM, Sarath , DUTTA, Deepanshu
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3427
摘要： Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells 200 comprises a plurality of word lines 260, 262, 264, 266, 506, 508, 510. A controller 126, 220 is configured to perform a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to a target word line 506. A controller 126, 220 is configured to determine a read setting for application to a target word line 506 based on a result of a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to the target word line 506. A controller 126, 220 is configured to perform a read operation on a target word line 506 using a determined read setting.
摘要翻译：公开了用于状态相关读取补偿的设备，系统，方法和计算机程序产品。一组非易失性存储单元200包括多个字线260,262,264,266,506,508,510。控制器126,220被配置为对一个或多个字线260,262执行读操作控制器126,220被配置为基于在一个或多个字线506上的读取操作的结果来确定用于施加到目标字线506的读取设置邻近目标字线506的控制器260,262,264,266,508,510。控制器126,220被配置为使用确定的读取设置对目标字线506执行读取操作。

42. 发明申请

WO2018004836A1 METHODS AND APPARATUS TO REDUCE THRESHOLD VOLTAGE DRIFT 审中-公开
标题翻译：减少阈值电压漂移的方法和设备
公开(公告)号：WO2018004836A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/031985
申请日：2017-05-10
申请人： INTEL CORPORATION
发明人： MANTEGAZZA, Davide , PAN, Feng , DAMLE, Prashant S. , BELGAL, Hanmant Pramod , PANGAL, Kiran
IPC分类号： G11C13/00
CPC分类号： G11C16/3427 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2013/0052 , G11C2013/0057 , G11C2013/0092 , G11C2213/76 , H01L27/2481 , H01L45/06
摘要： A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.
摘要翻译：所公开的用于降低存储器单元的选择器器件的阈值电压漂移的示例包括向存储器单元的选择器器件提供施加的电压，所施加的电压小于阈值电压的阈值电压通过将选择器装置处施加的电压维持阈值持续时间以激活选择器装置，从而降低存储器单元的阈值电压漂移。

43. 发明申请

WO2017218170A1 METHOD AND APPARATUS FOR PROGRAMMING WORDLINES OF NAND FLASH MEMORY USING ALTERNATING ENCODING SCHEMES 审中-公开
标题翻译：使用交替编码方案编程NAND闪存的术语的方法和设备
公开(公告)号：WO2017218170A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/034911
申请日：2017-05-29
申请人： INTEL CORPORATION
发明人： ZHANG, Nuo , KALAVADE, Pranav , PARAT, Krishna
IPC分类号： G11C16/08 , G11C16/04 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C2211/5641 , G11C2211/5648
摘要： In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to program a plurality of cells of a first wordline of the NAND flash memory to cause a programmed cell of the first wordline to store a first number of bits; and program a plurality of cells of a second wordline that is adjacent to the first wordline, to cause a programmed cell of the second wordline to store a second number of bits, wherein the first number and the second number are different.
摘要翻译：在一个实施例中，一种装置包括包含NAND快闪存储器的存储装置。存储设备将对NAND闪存的第一字线的多个单元进行编程以使第一字线的编程单元存储第一数量的比特; 以及对与第一字线相邻的第二字线的多个单元进行编程，以使得第二字线的编程单元存储第二数量的比特，其中第一数目和第二数目是不同的。

44. 发明申请

WO2017075442A1 DATA RETENTION CHARGE LOSS AND READ DISTURB COMPENSATION IN SOLID-STATE DATA STORAGE SYSTEMS 审中-公开
标题翻译：在固态数据存储系统中的数据保留电荷损失和读取扰动补偿
公开(公告)号：WO2017075442A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/059454
申请日：2016-10-28
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： MAIN, Dale Charles , KASHYAP, Abhilash Ravi
IPC分类号： G11C16/10 , G11C16/34 , G11C16/26 , G06F12/02
CPC分类号： G11C29/50004 , G06F3/0604 , G06F3/0647 , G06F3/0652 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C29/50016 , G11C2029/5004
摘要： A data storage device includes a solid-state memory including memory cells and a controller that performs a first programming scheme that programs a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.
摘要翻译：数据存储装置包括固态存储器，所述固态存储器包括存储器单元和控制器，所述控制器执行使用第一目标电压将单元的第一子集编程到第一电压状态的第一编程方案，编程使用高于所述第一目标电压的第二目标电压将第二子集切换到第二电压状态，使用高于所述第二目标电压的第三目标电压将第三子集编程到第三电压状态，并且将第四子集编程到第四电压使用比第三目标电压高的第四目标电压。第四目标电压与第三目标电压之间的电压差可以大于或小于第三目标电压与第二目标电压之间的电压差和/或第二目标电压与第一目标电压之间的电压差电压。

45. 发明申请

WO2017053460A1 WEIGHTED PROGRAMMING PATTERNS IN SOLID-STATE DATA STORAGE SYSTEMS 审中-公开
标题翻译：固态数据存储系统中加权编程模式
公开(公告)号：WO2017053460A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/052928
申请日：2016-09-21
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： KASHYAP, Abhilash Ravi , MAIN, Dale Charles
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G06F3/06
CPC分类号： G06F3/0619 , G06F3/0632 , G06F3/0679 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3427
摘要： Systems and methods are disclosed for programming data in non-volatile memory arrays. A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller configured to improve data retention or reduce read disturb of at least a portion of the solid-state non-volatile memory at least in part by receiving data to be written to the solid-state non-volatile memory. The controller is further configured to, when a data retention programming mode is set, encode the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower voltage level than the second programming state, and write the encoded data to the solid-state non-volatile memory. When a read disturb programming mode is set, the first programming state is associated with a higher voltage level than the second programming state.
摘要翻译：公开了用于在非易失性存储器阵列中编程数据的系统和方法。数据存储设备包括固态非易失性存储器，其包括多个存储器单元，以及控制器，其被配置为至少部分地通过以下方式改进至少一部分固态非易失性存储器的数据保持或减少读取干扰：接收要写入固态非易失性存储器的数据。控制器还被配置为当设置数据保留编程模式时，使用在第二编程状态下有利于第一编程状态的编程模式对数据进行编码，所述第一编程状态与比第二编程的低电压电平相关联状态，并将编码数据写入固态非易失性存储器。当设置读取干扰编程模式时，第一编程状态与比第二编程状态更高的电压电平相关联。

46. 发明申请

WO2016081064A1 NAND BOOSTING USING DYNAMIC RAMPING OF WORD LINE VOLTAGES 审中-公开
标题翻译：使用文字线电压的动态斜率进行NAND升压
公开(公告)号：WO2016081064A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/052066
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： RABKIN, Peter , DONG, Yingda , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
摘要翻译：描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时存储器阵列和存储器阵列内的未选择字线组的位置。

47. 发明申请

WO2016063592A1 メモリコントローラ、メモリシステム、および、メモリコントローラの制御方法审中-公开
标题翻译：存储器控制器，存储器系统和存储器控制器控制方法
公开(公告)号：WO2016063592A1
公开(公告)日：2016-04-28
申请号：PCT/JP2015/070829
申请日：2015-07-22
申请人：ソニー株式会社
发明人：新橋　龍男 , 筒井　敬一 , 大久保　英明 , 阪井　塁 , 中西　健一 , 藤波　靖
IPC分类号： G06F12/16 , G11C13/00
CPC分类号： G06F11/004 , G06F3/0619 , G06F12/16 , G11C7/1006 , G11C13/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C29/52
摘要：　メモリセルにおいて誤りの発生頻度を十分に低減する。　読出し部が、情報ビットと情報ビットが反転されているか否かを判定するための反転情報とを含むリードデータをメモリセルから読み出す。また、誤り検出訂正部が、その情報ビットの誤りの有無を検出して誤りを訂正する。データ反転部が、誤りが訂正された情報ビットと反転情報とを反転する。また、書込み部が、反転された情報ビットと反転された反転情報とを前記メモリセルに書き込む。
摘要翻译：本发明的目的是充分降低存储单元中的错误发生频率。读出单元从存储单元读出包含用于确定信息位是否反转的信息位和反相信息的数据。错误检测和校正单元检测信息位中是否存在错误并纠正错误。数据反转单元反转纠错错误的信息位和反转信息。写单元向存储器单元写入反相信息位和反转反转信息。

48. 发明申请

WO2016053553A1 LATCH INITIALIZATION FOR A DATA STORAGE DEVICE 审中-公开
标题翻译：数据存储设备的锁存初始化
公开(公告)号：WO2016053553A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047967
申请日：2015-09-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： LASSER, Menahem
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/20 , G11C7/1006 , G11C7/1009 , G11C7/1087 , G11C11/5614 , G11C11/5628 , G11C11/5671 , G11C13/0033 , G11C13/0069 , G11C16/10 , G11C16/3427
摘要： A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information.
摘要翻译：数据存储设备可以包括存储器管芯。存储器管芯包括存储器和锁存器。方法可以包括接收与写入操作相对应的命令以将信息写入存储器。该方法还可以包括在接收存储器管芯之前的信息时将一组位加载到锁存器中。所述位组包括具有第一值的至少第一位和具有不同于第一值的第二值的第二位。所述方法还包括在所述存储器管芯处接收所述信息，并用所述信息重写所述锁存器中的所述一组位的至少一部分。

49. 发明申请

WO2015054338A1 SYSTEM AND METHOD OF STORING DATA IN A DATA STORAGE DEVICE WITH A SELECTION OF TWO WRITING ORDERS IN ORDER TO IMPROVE THE READING SPEED OF A DIFFERENTIAL LOOK AHEAD READING MODE. 审中-公开
标题翻译：在数据存储设备中存储数据的系统和方法，其具有选择两个写入顺序以提高差异性前景读取模式的读取速度。
公开(公告)号：WO2015054338A1
公开(公告)日：2015-04-16
申请号：PCT/US2014/059608
申请日：2014-10-08
申请人： SANDISK TECHNOLOGIES INC.
发明人： LASSER, Menahem
IPC分类号： G11C7/10 , G11C11/56 , G11C16/34
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/3427 , G11C16/3436 , G11C2211/5646 , G11C2211/5648
摘要： A method that may be performed in a data storage device includes selecting a writing order for data to be written to a set of word lines of a block of a non-volatile memory. The data is organized in pages that are ordered according to a logical page address order. The writing order is selected from at least a first order or a second order that is distinct from the first order. Stored data in the non-volatile memory written according to the first order has logical page addresses that decrease with increasing values of word line physical addresses. The method also includes writing the data to the set of word lines according to the selected writing order and storing a flag value that indicates the selected writing order.
摘要翻译：可以在数据存储装置中执行的方法包括选择要写入到非易失性存储器的块的一组字线的数据的写入顺序。数据按照逻辑页面地址顺序排列的页面进行组织。写入顺序是从与第一顺序不同的至少第一顺序或第二顺序中选择的。根据第一级写入的非易失性存储器中的存储数据具有随着字线物理地址的增加而减小的逻辑页地址。该方法还包括根据所选择的写入顺序将数据写入字线组，并存储指示所选择的写入顺序的标志值。

50. 发明申请

WO2014137631A1 INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：用于非易失性存储的内部数据负载
公开(公告)号：WO2014137631A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/017846
申请日：2014-02-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： CHEN, Wenzhou , LEE, Dana , ZHENMING, Zhou , GUIRONG, Liang
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5648
摘要： Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides a cleaner lower page when later programming the upper page into the target memory cells.
摘要翻译：本文公开了用于执行内部数据加载（IDL）以感测非易失性存储元件的技术。可以调整施加到选定字线的两个相邻字线的读通过电压，以产生更准确的IDL。一个相邻的读取通过电压可以增加一些Δ电压，而另一个相邻的读取通过电压可以减小相同的delta电压。在一个方面，停止将数据的上部页面编程为与目标字线相邻的字线，以允许使用IDL读取目标存储器单元中的较低页面数据，并将其保存在数据锁存器中，同时对邻居词完成。当稍后将上部页面编程到目标存储器单元中时，保留下部页面数据提供了更干净的下部页面。

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