专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2015148870A1 RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING 审中-公开
标题翻译：在存储器编程期间放大禁止电压
公开(公告)号：WO2015148870A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022865
申请日：2015-03-27
申请人： INTEL CORPORATION
发明人： RAJWADE, Shantanu , KALAVADE, Pranav , MIELKE, Neal , PARAT, Krishna , RAGHUNATHAN, Shyam Sunder
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
摘要翻译：禁止电压是施加到与在程序操作期间具有要写入的存储器单元的程序字线相邻的字线的电压。在编程脉冲期间，编程操作的禁止电压可能会上升。代替施加恒定的高抑制电压，导致初始升压通道电位由于泄漏而急剧降低，系统可以将抑制电压降低，并在编程脉冲期间将抑制电压斜升。在编程脉冲期间，斜坡可以是连续斜坡或者有限的离散步长。抑制电压的这种斜坡可以在程序干扰和抑制干扰之间提供更好的权衡。

2. 发明申请

WO2019112712A1 METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH MEMORY 审中-公开
公开(公告)号：WO2019112712A1
公开(公告)日：2019-06-13
申请号：PCT/US2018/058606
申请日：2018-11-01
申请人： INTEL CORPORATION
发明人： ZHAO, Han , KALAVADE, Pranav , PARAT, Krishna
IPC分类号： G11C16/34 , G11C16/08 , G11C16/30
摘要： Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

3. 发明申请

WO2017218170A1 METHOD AND APPARATUS FOR PROGRAMMING WORDLINES OF NAND FLASH MEMORY USING ALTERNATING ENCODING SCHEMES 审中-公开
标题翻译：使用交替编码方案编程NAND闪存的术语的方法和设备
公开(公告)号：WO2017218170A1
公开(公告)日：2017-12-21
申请号：PCT/US2017/034911
申请日：2017-05-29
申请人： INTEL CORPORATION
发明人： ZHANG, Nuo , KALAVADE, Pranav , PARAT, Krishna
IPC分类号： G11C16/08 , G11C16/04 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C2211/5641 , G11C2211/5648
摘要： In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to program a plurality of cells of a first wordline of the NAND flash memory to cause a programmed cell of the first wordline to store a first number of bits; and program a plurality of cells of a second wordline that is adjacent to the first wordline, to cause a programmed cell of the second wordline to store a second number of bits, wherein the first number and the second number are different.
摘要翻译：在一个实施例中，一种装置包括包含NAND快闪存储器的存储装置。存储设备将对NAND闪存的第一字线的多个单元进行编程以使第一字线的编程单元存储第一数量的比特; 以及对与第一字线相邻的第二字线的多个单元进行编程，以使得第二字线的编程单元存储第二数量的比特，其中第一数目和第二数目是不同的。

4. 发明申请

WO2021155611A1 BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN MEMORY ARRAY 审中-公开
公开(公告)号：WO2021155611A1
公开(公告)日：2021-08-12
申请号：PCT/CN2020/074565
申请日：2020-02-08
申请人： INTEL CORPORATION , THIMMEGOWDA, Deepak , CLEEREMAN, Brian J. , GOWDA, Srivardhan , LIN, Jui-Yen , LIU, Liu , PARAT, Krishna , SEL, Jong Sun , ZHOU, Baosuo
发明人： THIMMEGOWDA, Deepak , CLEEREMAN, Brian J. , GOWDA, Srivardhan , LIN, Jui-Yen , LIU, Liu , PARAT, Krishna , SEL, Jong Sun , ZHOU, Baosuo
IPC分类号： H01L27/1157
摘要： An integrated circuit memory (100) includes a first memory block (102a) and an adjacent second memory block (102b). The first memory block (102a) comprises a first memory pillar (156a) around which a first memory cell is formed. The second memory block (102b) comprises a second memory pillar (156b) around which a second memory cell is formed. An isolation or slit area (104) between the first and second memory blocks (102a,102b) electrically isolates the first and second memory blocks (102a,102b). The slit area (104) comprising a slit pillar (124) around which no memory cells are formed. The slit pillar (124) is a dummy pillar, and insulator material electrically isolates the slit pillar (124) from a Word Line (WL) (120a,120b) through which it passes. The isolation layer electrically can also isolate a (WL)(120a) of the first memory block (102a) from a corresponding WL (120b) of the second memory block (102b). The slit pillar (124) and the memory pillars (156a,156b) have at least in part similar structures.

5. 发明申请

WO2007059239A1 METHOD OF FORMING NON-VOLATILE MEMORY CELL USING SACRIFICIAL PILLAR SPACERS AND NON-VOLATILE MEMORY CELL FORMED ACCORDING TO THE METHOD 审中-公开
标题翻译：根据方法形成非挥发性记忆细胞的非挥发性记忆细胞的形成方法
公开(公告)号：WO2007059239A1
公开(公告)日：2007-05-24
申请号：PCT/US2006/044397
申请日：2006-11-14
申请人： INTEL CORPORATION , SOSS, Steven, R. , PARAT, Krishna
发明人： SOSS, Steven, R. , PARAT, Krishna
IPC分类号： H01L21/336 , H01L29/788 , H01L21/28 , H01L29/423 , H01L21/762 , H01L21/8247
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A method of forming a icroelectronic non-volatile memory cell (200) , a memory-cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate (206) , providing a pair of spaced apart isolation bodies (201) on the substrate, the isolation bodies including respective raised isolation portions (222) , providing the pair comprising providing a buffer layer (221) on the substrate; providing pillar spacers (224) on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric (204) on the surface of the substrate after removing the buffer layer; providing a floating gate (202) on the tunnel dielectric; a reducing a height of the isolation bodies to yield corresponding isolation regions; providing source and drain regions on opposite sides of the floating gate,- providing an interpoly dielectric (208) on the floating gate; and providing a control gate (210) on the interpoly dielectric to yield the memory cell.
摘要翻译：一种形成微电子非易失性存储单元（200）的方法，根据该方法形成的存储单元和包括存储单元的系统。该方法包括：提供衬底（206），在衬底上提供一对间隔开的隔离体（201），所述隔离体包括相应的凸起隔离部分（222），提供该对包括提供缓冲层基材; 在凸起的隔离部分的侧壁上设置支柱间隔物（224）; 在提供柱间隔物之后去除缓冲层; 在移除缓冲层期间移除柱状间隔物; 在去除所述缓冲层之后，在所述衬底的表面上提供隧道电介质（204）; 在所述隧道电介质上提供浮动栅极（202）; 降低隔离体的高度以产生相应的隔离区域; 在所述浮动栅极的相对侧上提供源极和漏极区域; - 在所述浮动栅极上提供互补电介质（208）; 以及在所述互聚电介质上提供控制栅极（210）以产生所述存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式