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1. 发明申请

WO2018044368A1 STATE-DEPENDENT READ COMPENSATION 审中-公开
标题翻译：与状态相关的读取补偿
公开(公告)号：WO2018044368A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/033300
申请日：2017-05-18
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHOU, Zhenming , LIANG, Guirong , HEMINK, Gerrit Jan , LEE, Dana , GORLA, Chandu , PUTHENTHERMADAM, Sarath , DUTTA, Deepanshu
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3427
摘要： Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells 200 comprises a plurality of word lines 260, 262, 264, 266, 506, 508, 510. A controller 126, 220 is configured to perform a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to a target word line 506. A controller 126, 220 is configured to determine a read setting for application to a target word line 506 based on a result of a read operation on one or more word lines 260, 262, 264, 266, 508, 510 adjacent to the target word line 506. A controller 126, 220 is configured to perform a read operation on a target word line 506 using a determined read setting.
摘要翻译：公开了用于状态相关读取补偿的设备，系统，方法和计算机程序产品。一组非易失性存储单元200包括多个字线260,262,264,266,506,508,510。控制器126,220被配置为对一个或多个字线260,262执行读操作控制器126,220被配置为基于在一个或多个字线506上的读取操作的结果来确定用于施加到目标字线506的读取设置邻近目标字线506的控制器260,262,264,266,508,510。控制器126,220被配置为使用确定的读取设置对目标字线506执行读取操作。

2. 发明申请

WO2019216965A1 NON-VOLATILE MEMORY WITH MULTI-PLANE MIXED SUB-BLOCK PROGRAMMING 审中-公开
公开(公告)号：WO2019216965A1
公开(公告)日：2019-11-14
申请号：PCT/US2019/016719
申请日：2019-02-05
申请人： SANDISK TECHNOLOGIES LLC
发明人： CHIN, Henry , ZHOU, Zhenming
IPC分类号： G11C16/08 , G11C16/10 , G11C16/30 , G11C5/14 , G11C16/04
摘要： A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.

3. 发明申请

WO2017074576A1 SMART VERIFY FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：用于编程非易失性存储器的智能验证
公开(公告)号：WO2017074576A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051452
申请日：2016-09-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： DUNGA, Mohan , HEMINK, Gerrit Jan , ZHOU, Zhenming , HIGASHITANI, Masaaki
IPC分类号： G11C16/34
CPC分类号： G11C16/10 , G11C16/3459
摘要： Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.
摘要翻译：提供了用于在编程非易失性存储器时降低电流消耗的技术。使用存储器单元的子集来执行智能验证。通过将智能验证应用于存储单元的一个子集，节省了电流。智能验证可用于表征编程速度。智能验证的结果可以用于确定稍后在编程过程中将应用的伪编程脉冲的幅度。伪编程脉冲之后没有编程验证，这会减少电流。如果伪编程脉冲将阈值电压推得足够高，那么稍后在编程中验证时，这些存储单元将不会传导电流。因此，在编程验证期间保存电流。此外，接收虚拟脉冲的存储单元的位线在编程脉冲之前不需要预充电，这可以节省更多电流。

4. 发明申请

WO2019240860A1 SUBGROUP SELECTION FOR VERIFICATION 审中-公开
公开(公告)号：WO2019240860A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/023763
申请日：2019-03-22
申请人： SANDISK TECHNOLOGIES LLC
发明人： LIEN, Yu-Chung , YANG, Xiang , ZHOU, Zhenming , DUTTA, Deepanshu , TSENG, Huai-Yuan
IPC分类号： G11C16/34 , G11C16/10 , G11C16/14
摘要： An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

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