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31. 发明申请

WO2018175097A1 APPARATUS AND METHOD FOR LATCHING DATA INCLUDING AND-NOR OR OR-NAND GATE AND FEEDBACK PATHS 审中-公开
公开(公告)号：WO2018175097A1
公开(公告)日：2018-09-27
申请号：PCT/US2018/020881
申请日：2018-03-05
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Changho , YANG, Derek , YOON, Sei Seung
IPC分类号： H03K3/012 , H03K3/037 , H03K19/0948 , H03K19/20 , H03K19/003
摘要： A latch circuit (200) includes an AND-NOR gate (210), a NAND gate (230), and a NOR gate (220). The AND-NOR gate includes a first AND-input configured to receive input data (DIN) and a second AND- input coupled to an output (A) of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output (B) of the NOR gate, and an output configured to generate output data (Dout). The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal (CLK). The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal (CLK/). During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

32. 发明申请

WO2017189175A1 NOVEL MEMORY CELL WITH IMPROVED WRITE MARGIN 审中-公开
标题翻译：具有改进的写入边缘的新型存储单元
公开(公告)号：WO2017189175A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/025519
申请日：2017-03-31
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Changho , KIM, Keejong , YOON, Sei Seung
IPC分类号： G11C11/412 , G11C11/419 , G11C8/14 , G11C8/16 , H01L27/02 , H01L27/11
CPC分类号： G11C11/419 , G11C8/14 , G11C8/16 , G11C11/412 , G11C11/4125 , H01L28/00
摘要： A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.
摘要翻译：提供了一种用于操作存储器的存储器和方法。存储器包括存储单元，该存储单元具有存储位的第一电路和用于将存储的位与电源和返回去耦的第二电路。该方法包括通过第一电路将位存储在存储器单元中，并且将所存储的位与电源解耦以及通过第二电路解耦。提供另一个内存。该存储器包括具有用于通过反馈存储位的装置的存储单元和用于禁止反馈的装置。

33. 发明申请

WO2017136106A1 SENSE AMPLIFIER RANDOM NOISE STRESS 审中-公开
标题翻译： SENSE AMPLIFIER随机噪声应力
公开(公告)号：WO2017136106A1
公开(公告)日：2017-08-10
申请号：PCT/US2017/012756
申请日：2017-01-09
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , AHMED, Fahad , YOON, Sei Seung , KIM, Keejong
IPC分类号： G11C29/02 , G11C29/50 , G11C29/14 , G11C7/02 , G11C11/419
CPC分类号： G11C7/02 , G11C5/06 , G11C7/00 , G11C7/062 , G11C7/08 , G11C7/10 , G11C7/14 , G11C11/418 , G11C11/419 , G11C29/02 , G11C29/026 , G11C29/14 , G11C29/50012
摘要： A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.
摘要翻译：存储器包括存储器单元，耦合到存储器单元的一条位线，耦合到所述一条位线的读出放大器，被配置为在读取操作期间启用读出放大器的定时电路，配置成控制电路以使读出放大器独立于定时电路;以及上拉电路，被配置为在读出放大器被控制电路使能的同时上拉一个位线。该方法包括通过定时电路使读出放大器处于读取操作中。读出放大器耦合到至少一个位线，并且该至少一个位线耦合到存储器单元。该方法进一步包括在第二操作中使读出放大器独立于定时电路并且在读出放大器在第二操作中被使能的同时通过上拉电路拉起至少一个位线。

34. 发明申请

WO2016039855A1 EFFICIENT CODING FOR MEMORY REDUNDANCY 审中-公开
标题翻译：高效记忆冗余编码
公开(公告)号：WO2016039855A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/041250
申请日：2015-07-21
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , YOON, Sei Seung , HOEM, Robert Henry
IPC分类号： G11C29/00 , G11C8/12 , G11C8/10
CPC分类号： G11C29/781 , G11C8/10 , G11C8/12 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/76 , G11C29/802 , G11C29/806
摘要： A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.
摘要翻译：可以提供为诸如SRAM之类的多个嵌入存储器提供冗余的系统。系统可以包括一个或多个解码器，每个解码器能够解码选择地址以识别嵌入存储器中的有缺陷的一个。

35. 发明申请

WO2013122884A1 POWER-ON-RESET (POR) CIRCUITS FOR RESETTING MEMORY DEVICES, AND RELATED CIRCUITS, SYSTEMS, AND METHODS 审中-公开
标题翻译：用于复位存储器件的上电复位（POR）电路以及相关电路，系统和方法
公开(公告)号：WO2013122884A1
公开(公告)日：2013-08-22
申请号：PCT/US2013/025607
申请日：2013-02-11
申请人： QUALCOMM INCORPORATED
发明人： TERZIOGLU, Esin , GANESAN, Balachander , PARK, Alex Dongkyu , YOON, Sei Seung
IPC分类号： G11C7/20 , G11C8/10
CPC分类号： G11C8/10 , G11C7/20
摘要： Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.
摘要翻译：公开了用于重置存储器件的上电复位（POR）电路以及相关电路，系统和方法。在一个实施例中，提供了一个POR电路。 POR电路被配置为从至少一个存储器解码装置接收多个解码的地址输出作为输入。 POR电路还被配置为如果多个解码的地址输出中的任一个是有效的，则产生POR复位。结果，存储器解码装置锁存器可以被重置为已知的默认条件，以避免在外部复位可用之前在上电状态期间在存储器中引起无意的字线选择。由于POR电路可以在不需要外部复位的情况下生成POR复位，所以可以快速复位存储器解码器件，以便在上电状态后可以更快地提供存储器的可用性。

36. 发明申请

WO2019060120A1 FLEXIBLE MEMORY ASSISTANCE SCHEME 审中-公开
公开(公告)号：WO2019060120A1
公开(公告)日：2019-03-28
申请号：PCT/US2018/048808
申请日：2018-08-30
申请人： QUALCOMM INCORPORATED
发明人： TERZIOGLU, Esin , YOON, Sei Seung , JUNG, Chulmin , LIANG, Bin
IPC分类号： G11C11/419 , G11C11/418
摘要： In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.

37. 发明申请

WO2018048576A1 LOWER POWER HIGH SPEED DECODING BASED DYNAMIC TRACKING FOR MEMORIES 审中-公开
标题翻译：低功耗高速解码的基于动态追踪的记忆
公开(公告)号：WO2018048576A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/046616
申请日：2017-08-11
申请人： QUALCOMM INCORPORATED
发明人： LIANG, Bin , KWOK, Tony Chung Yiu , LI, Rui , YOON, Sei Seung
IPC分类号： G11C7/22 , G11C8/18 , G11C11/418 , G11C11/419
摘要： A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.
摘要翻译：公开了一种存储器。存储器包括具有多个存储器单元的存储器阵列。存储器还包括地址解码器，其被配置为断言字线以启用存储器单元。另外，存储器包括跟踪电路，该跟踪电路被配置为根据哪个存储器单元被访问来改变断言字线的持续时间。还公开了一种方法。该方法包括断言字线以启用存储器单元并根据多个存储器单元中的哪一个被访问而改变断言字线的持续时间。

38. 发明申请

WO2017184279A1 SYSTEMS AND METHODS TO PROVIDE SECURITY TO ONE TIME PROGRAM DATA 审中-公开
标题翻译：提供一次性程序数据安全性的系统和方法
公开(公告)号：WO2017184279A1
公开(公告)日：2017-10-26
申请号：PCT/US2017/023056
申请日：2017-03-17
申请人： QUALCOMM INCORPORATED
发明人： KOTA, Anil , YOON, Sei Seung , KUBENDRAN, Bhadri
IPC分类号： G11C17/14 , G06F21/78
摘要： A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.
摘要翻译：一种方法包括：从处理芯片的一次编程（OTP）存储器读取多个单词，其中每个单词包括用于芯片的安全数据和与检查模式相对应的位 ; 将对应于检查模式的位与预编程的检查模式进行比较; 基于将对应于检查模式的比特与预编程的检查模式进行比较来检测错误; 并且响应于检测到错误而由处理芯片执行动作。

39. 发明申请

WO2016175969A1 SENSE AMPLIFIER WITH PULSED CONTROL 审中-公开
标题翻译：具有脉冲控制的感应放大器
公开(公告)号：WO2016175969A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/024772
申请日：2016-03-29
申请人： QUALCOMM INCORPORATED
发明人： AHMED, Fahad , JUNG, Chulmin , YOON, Sei Seung
IPC分类号： G11C7/06 , G11C7/08 , G11C11/419
CPC分类号： G11C11/419 , G11C7/062 , G11C7/065 , G11C7/08 , G11C7/12
摘要： A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.
摘要翻译：读出放大器设置有一对第一上拉晶体管，其被配置为对相应的一对输出端子充电，同时延迟感测使能信号未被置位并且在延迟的感测使能信号的同时停止对相应的输出端子对的充电被断言。

40. 发明申请

WO2016149333A1 HIGH-SPEED WORD LINE DECODER AND LEVEL-SHIFTER 审中-公开
标题翻译：高速字线解码器和电平变换器
公开(公告)号：WO2016149333A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/022593
申请日：2016-03-16
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , CHEN, Po-Hung , LI, David , YOON, Sei Seung
IPC分类号： G11C8/10
CPC分类号： G11C8/08 , G11C5/14 , G11C8/06 , G11C8/10
摘要： A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.
摘要翻译：提供了一种存储器，其包括行解码器，其将地址解码为用于从多个字线选择要断言的字线的多个解码信号。每个字线通过处理解码信号的解码器电平转换器驱动。每个解码器电平转换器对应于解码信号的唯一组合。行解码器处于逻辑功率域，使得解码信号被断言为逻辑电源电压。当解码器电平移位器的解码信号的唯一组合由行解码器确定时，解码器电平转换器用存储器电源域的存储器电源电压驱动相应的字线。

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