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1. 发明申请

WO2015171274A1 DUAL IN LINE MEMORY MODULE (DIMM) CONNECTOR 审中-公开
标题翻译：双线存储模块（DIMM）连接器
公开(公告)号：WO2015171274A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/025772
申请日：2015-04-14
申请人： QUALCOMM INCORPORATED
发明人： BERRY JR., Robert Walter , PENNINGTON, Ryan Joseph , HENDERSON, Joab Daniel , KUMAR, Divya
IPC分类号： G06F13/16 , G06F13/40 , G06F11/07
CPC分类号： H01R12/7076 , G06F11/008 , G06F11/07 , G06F11/2094 , G06F13/1668 , G06F13/409 , G11C5/04 , G11C29/781 , G11C29/832
摘要： An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.
摘要翻译：增强型双列直插式存储器模块（DIMM）连接器包括内部导电路径，可在通向工业标准DIMM的标准导电路径上访问信号。内部导电路径与通过连接器的标准导电路径串联或并联耦合。插入器电路，例如控制电路和/或补充存储器电路，可以被结合在连接器上或连接器内。插入器电路可以包括场效应晶体管（FET）开关电路，其被配置为选择性地将DIMM上的有缺陷的动态随机存储器（DRAM）从导电路径分离到存储器控制器，并将替代DRAM耦合到其位置的导电路径。

2. 发明申请

WO01029668A1 REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY 审中-公开
标题翻译：冗余双银行架构，用于同时操作闪存
公开(公告)号：WO01029668A1
公开(公告)日：2001-04-26
申请号：PCT/US2000/027911
申请日：2000-10-09
IPC分类号： G06F12/16 , G11C16/06 , G11C29/00 , G11C29/04 , G06F11/20
CPC分类号： G11C29/781 , G11C2216/22
摘要： The present invention discloses sector-based redundancy that is capable of making repairs using a plurality of redundant columns of memory cells in a dual bank memory device during simultaneous operation. The simultaneous operation memory device includes a plurality of redundant blocks (18) that can be configured to be located in an upper bank (20) or a sliding lower bank (22). The redundant blocks (18) are comprised of sectors (12) and each sectors (12) and each sector (12) contains columns of memory cells (26). During simultaneous operation, the memory device is capable of reading the columns of memory cells (26) in one bank and writing columns of memory cells (26) in the other bank at the same time. In addition, the simultaneous operation memory device uses sector-based redundancy to repair columns of memory cells (26) that are defective in one bank by electrically exchanging them with redundant columns of memory cells (34) and, at the same time, repair columns of memory cells (26) that are defective in the other bank. The dual bank sector-based redundancy includes a plurality of address CAM circuits (54) that are configurably associated with the redundant blocks (18) based on the blank location of the redundant blocks (18). The address CAM circuits (54) are configured by a redundancy CAM read drain decoder circuit (50).
摘要翻译：本发明公开了基于扇区的冗余，其能够在同时操作期间使用双组存储器设备中的多个冗余列的存储单元进行修复。同时操作存储装置包括多个冗余块（18），其可被配置为位于上层（20）或滑动式下层（22）中。冗余块（18）由扇区（12）和每个扇区（12）组成，每个扇区（12）包含存储单元列（26）。在同时操作期间，存储器件能够读取一个存储体中的存储单元（26）的列并且同时在另一个存储体中写入存储单元（26）的列。此外，同时操作存储装置使用基于扇区的冗余来通过与存储单元（34）的冗余列电交换来修复在一个存储体中有缺陷的存储单元（26）的列，并且同时修复列的存储单元（26）在另一个库中有缺陷。基于双银行部门的冗余包括基于冗余块（18）的空白位置而与冗余块（18）可配置地相关联的多个地址CAM电路（54）。地址CAM电路（54）由冗余CAM读取漏极解码电路（50）构成。

3. 发明申请

WO2018067262A1 NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE 审中-公开
标题翻译：具有宽I / O存储器模块的非易失性存储器系统
公开(公告)号：WO2018067262A1
公开(公告)日：2018-04-12
申请号：PCT/US2017/050432
申请日：2017-09-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： RAMACHANDRA, Venkatesh P. , MOSTOVOY, Michael , TAKIAR, Hem , KUMAR, Gokul , GHATAWADE, Vinayak
IPC分类号： G11C7/10 , G11C5/06 , G11C5/04 , G06F13/42 , G06F13/40 , H01L25/065
CPC分类号： H01L25/0657 , G06F13/4018 , G06F13/4234 , G11C5/04 , G11C5/063 , G11C5/066 , G11C7/065 , G11C7/10 , G11C7/22 , G11C29/781 , G11C2207/105 , G11C2207/108 , H01L25/18 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06582 , H01L2924/1431 , H01L2924/1434
摘要： A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.
摘要翻译：非易失性存储系统包括多个存储器管芯和接口电路。每个存储器裸片包括电耦合到多个存储器裸片中的另一个存储器裸片的另一宽I / O接口的宽I / O接口。接口电路与存储器管芯在物理上是分开的。接口电路包括第一接口和第二接口。第一接口包括电耦合到多个存储器管芯的至少一个存储器管芯的宽I / O接口的宽I / O接口。第二个接口是配置为与外部电路通信的窄I / O接口。

4. 发明申请

WO1980001732A1 MEMORY WITH REDUNDANT ROWS AND COLUMNS 审中-公开
标题翻译：具有冗余线和列的记忆
公开(公告)号：WO1980001732A1
公开(公告)日：1980-08-21
申请号：PCT/US1980000072
申请日：1980-01-28
申请人： WESTERN ELECTRIC CO INC
发明人： WESTERN ELECTRIC CO INC , PROCYK F , CENKER R
IPC分类号： G11C11/40
CPC分类号： G11C29/781
摘要： A memory is provided with standard rows and columns and spare rows (14) and columns (13) for substitution for standard rows and columns found to have defective cells. Each of the decoders (15, 16) associated with a standard row and/or column includes provision for being disconnected if found to be associated with a defective row or column. Each of the decoders (30) associated with a spare row and/or column is designed normally to be deselected for any address but to be able to assume the address of any disconnected row or column. Disconnection of the standard decoders (20) and substitution of the spare decoders (30) are made possible by appropriate inclusion of fusible links (21, 41) which can be selectively opened by laser irradiation.

5. 发明申请

WO2016039855A1 EFFICIENT CODING FOR MEMORY REDUNDANCY 审中-公开
标题翻译：高效记忆冗余编码
公开(公告)号：WO2016039855A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/041250
申请日：2015-07-21
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , YOON, Sei Seung , HOEM, Robert Henry
IPC分类号： G11C29/00 , G11C8/12 , G11C8/10
CPC分类号： G11C29/781 , G11C8/10 , G11C8/12 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/76 , G11C29/802 , G11C29/806
摘要： A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.
摘要翻译：可以提供为诸如SRAM之类的多个嵌入存储器提供冗余的系统。系统可以包括一个或多个解码器，每个解码器能够解码选择地址以识别嵌入存储器中的有缺陷的一个。

6. 发明申请

WO1996031825A1 MEMORY MANAGEMENT 审中-公开
标题翻译：内存管理
公开(公告)号：WO1996031825A1
公开(公告)日：1996-10-10
申请号：PCT/GB1996000320
申请日：1996-02-14
申请人： MEMORY CORPORATION PLC , DEAS, Alexander, Roger
发明人： MEMORY CORPORATION PLC
IPC分类号： G06F11/20
CPC分类号： G11C29/76 , G11C29/781
摘要： A device for replacing defective storage locations with working storage locations comprises receiving means for receiving an incoming address for accessing a storage location, comparing means for comparing the incoming address with all of the addresses of known defective storage locations, and directing means for directing accesses to an alternative location when the incoming address matches one of the addresses of known defective storage locations. There is one alternative storage location and one comparing means for each known defective storage location. In this invention only a portion of the incoming address is used in the comparing means. In addition, each of the comparing means may use a different portion of the address for accessing a storage location.
摘要翻译：用于用工作存储位置替换不良存储位置的装置包括用于接收用于访问存储位置的输入地址的接收装置，用于将输入地址与已知不良存储位置的所有地址进行比较的比较装置，以及用于将访问指向当输入地址与已知的有缺陷的存储位置的一个地址相匹配时的替代位置。对于每个已知的有缺陷的存储位置，存在一个替代存储位置和一个比较装置。在本发明中，在比较装置中仅使用输入地址的一部分。此外，每个比较装置可以使用地址的不同部分来访问存储位置。

7. 发明申请

WO1993021578A1 INTEGRATED SEMICONDUCTOR MEMORY WITH REDUNDANCY ARRANGEMENT 审中-公开
标题翻译：冗余设备集成的半导体存储器
公开(公告)号：WO1993021578A1
公开(公告)日：1993-10-28
申请号：PCT/DE1992000316
申请日：1992-04-16
申请人： SIEMENS AKTIENGESELLSCHAFT , RIEGER, Johann , STECKER, Johann
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F11/16
CPC分类号： G11C29/781 , G11C29/806 , G11C29/808 , G11C29/846
摘要： An integrated semiconductor memory has a block decoder BKDEC with block selection signals BKS and several individually actuable memory field block units BK. The memory field block units BK have memory cells that can be driven by word and bit lines NWL, NBL, N &cir& NOt B &cir& NOt L &cir& NOt and redundant memory cells RMC that can be driven by redundant word lines RWL. The memory field block units BK have programmable redundant block decoders RBK that allow, together with redundant word line decoders RWDEC, redundant word lines RWL to be selected. When a redundant word line RWL is to be selected, only the memory field block unit BK in which the redundant word line RWL to be selected is contained is activated, thus suppressing the otherwise usual activation by means of a corresponding block selection signal BKS. The redundant word line RWL to be selected, together with its redundant memory cells RMC, needs therefore not be located in the same memory field block unit BK as the memory cells to be replaced, together with their normal word line NWL, but may also be located in (any) other memory field block unit BK. Integrated semiconductor memories may thus be produced with a higher yield.

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