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1. 发明申请

WO2023034576A1 SRAM DESIGN FOR ENERGY EFFICIENT SEQUENTIAL ACCESS 审中-公开
公开(公告)号：WO2023034576A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/042466
申请日：2022-09-02
申请人： META PLATFORMS TECHNOLOGIES, LLC
发明人： DALLARD, Edith , LIU, Huichu , MORRIS, Daniel Henry
IPC分类号： G11C7/10 , G11C11/418 , G11C11/419
摘要： An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

2. 发明申请

WO2019060120A1 FLEXIBLE MEMORY ASSISTANCE SCHEME 审中-公开
公开(公告)号：WO2019060120A1
公开(公告)日：2019-03-28
申请号：PCT/US2018/048808
申请日：2018-08-30
申请人： QUALCOMM INCORPORATED
发明人： TERZIOGLU, Esin , YOON, Sei Seung , JUNG, Chulmin , LIANG, Bin
IPC分类号： G11C11/419 , G11C11/418
摘要： In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.

3. 发明申请

WO2018048576A1 LOWER POWER HIGH SPEED DECODING BASED DYNAMIC TRACKING FOR MEMORIES 审中-公开
标题翻译：低功耗高速解码的基于动态追踪的记忆
公开(公告)号：WO2018048576A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/046616
申请日：2017-08-11
申请人： QUALCOMM INCORPORATED
发明人： LIANG, Bin , KWOK, Tony Chung Yiu , LI, Rui , YOON, Sei Seung
IPC分类号： G11C7/22 , G11C8/18 , G11C11/418 , G11C11/419
摘要： A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.
摘要翻译：公开了一种存储器。存储器包括具有多个存储器单元的存储器阵列。存储器还包括地址解码器，其被配置为断言字线以启用存储器单元。另外，存储器包括跟踪电路，该跟踪电路被配置为根据哪个存储器单元被访问来改变断言字线的持续时间。还公开了一种方法。该方法包括断言字线以启用存储器单元并根据多个存储器单元中的哪一个被访问而改变断言字线的持续时间。

4. 发明申请

WO2017172150A1 WORDLINE ADJUSTMENT SCHEME 审中-公开
标题翻译： WORDLINE调整计划
公开(公告)号：WO2017172150A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019488
申请日：2017-02-24
申请人： QUALCOMM INCORPORATED
发明人： SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C8/08 , G11C11/413 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/412 , G11C11/413 , G11C11/418 , G11C16/08 , G11C16/30
摘要： A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.
摘要翻译：提供了一种用于操作存储器的存储器和方法。存储器包括具有晶体管的存储器单元和输出耦合到存储器单元的字线的字线驱动器。字线驱动器调整字线的电压电平以补偿晶体管的参数。该方法包括断言字线电压以访问具有晶体管的存储器单元并且调整字线电压以补偿晶体管的参数。提供另一个内存。存储器包括存储器单元和输出耦合到存储器单元的字线的字线驱动器。字线驱动器基于字线的反馈来调整字线的电压电平。

5. 发明申请

WO2015027028A1 MEMORY WITH MULTIPLE WORD LINE DESIGN 审中-公开
标题翻译：具有多个字线设计的记忆
公开(公告)号：WO2015027028A1
公开(公告)日：2015-02-26
申请号：PCT/US2014/052024
申请日：2014-08-21
申请人： QUALCOMM INCORPORATED
发明人： GULATI, Chirag , SINHA, Rakesh Kumar , CHABA, Ritu , YOON, Sei Seung
IPC分类号： G11C11/412 , G11C11/418
CPC分类号： G11C11/419 , G11C8/14 , G11C8/16 , G11C11/412 , G11C11/418
摘要： Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.
摘要翻译：公开了具有多重读取字线设计的存储器的各种装置和方法。存储器可以包括排列成行的多个比特单元，连接到多个比特单元的第一子集的第一读取字线和连接到多个比特单元的第二子集的第二读取字线，其中第一和第二子集位于同一行位单元格中。一种方法可以包括在第一读取操作期间断言连接到排列在位单元行中的多个位单元的第一子集的第一读取字线，并且在第二读取操作期间断言第二读取字线连接到所述多个位单元的第二子集，其中所述第一和第二子集位于同一行比特单元中。

6. 发明申请

WO2014070702A1 DUMMY READ TO PREVENT CROWBAR CURRENT DURING READ-WRITE COLLISIONS IN MEMORY ARRAYS WITH CROSSCOUPLED BITLINE KEEPERS 审中-公开
标题翻译：在使用CROSSCOUPLED BITLINE KEEPERS的存储器阵列中阅读写入冲突之前，请务必阅读并防止曲线电流
公开(公告)号：WO2014070702A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/067193
申请日：2013-10-29
申请人： QUALCOMM INCORPORATED
发明人： SHANKAR, Harish , HOFF, David Paul , GARG, Manish
IPC分类号： G11C8/16 , G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/412 , G11C5/063 , G11C8/08 , G11C8/16 , G11C11/413 , G11C11/418
摘要： Systems and methods for detecting and suppressing crowbar currents in memory arrays (200). A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers (208a-b). When a simultaneous read and write operation to a first entry (202i) of the memory array is detected, the read operation (206i) to the first entry is suppressed and a dummy read operation (206j) to a second entry (202j) of the memory array is performed. The write operation (204i) to the first entry is allowed to proceed undisturbed.
摘要翻译：用于检测和抑制存储器阵列中的撬棒电流的系统和方法（200）。在具有交叉耦合位线保持器（208a-b）的静态随机存取存储器（SRAM）阵列中，在同时读写冲突的情况下，实现虚拟读取以防止撬棒电流。当检测到对存储器阵列的第一条目（202i）的同时读取和写入操作时，对第一条目的读取操作（206i）被抑制，并且虚拟读取操作（206j）到第二条目执行存储器阵列。允许对第一条目的写入操作（204i）不受干扰地进行。

7. 发明申请

WO2003015101A2 RANDOM-ACCESS MEMORY DEVICES COMPRISING A DIODED BUFFER 审中-公开
标题翻译：包含二极体缓冲器的随机存取存储器件
公开(公告)号：WO2003015101A2
公开(公告)日：2003-02-20
申请号：PCT/IB2002/003331
申请日：2002-08-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , STOJANOV, Nikola
发明人： STOJANOV, Nikola
IPC分类号： G11C11/418
CPC分类号： G11C8/08
摘要： Random-access memory device (20) comprising select lines (27; 47), bit lines (21.1 - 21.3), and several RAM cells (22.1 - 22.3), each RAM cell (22.1 - 22.3) being connected to a corresponding one of said select lines (27; 47)and to a corresponding one of said bit lines (21.1 - 21.3). The random-access memory device (20) further comprises select buffers (26; 46) for selecting the read-out of one out of the select lines (27; 47) when receiving a selection signal. Each of the select buffers (26; 46) comprises an inverter (29) serving as driver. The inverter (29) is being followed by a diode (30) for limiting output voltage swings at the respective select line (27; 47).
摘要翻译：包括选择线（27; 47），位线（21.1-2.3.3）和几个RAM单元（22.1-22.3）的随机存取存储器件（20），每个RAM单元（22.1-22.3）连接到所述选择线（27; 47）和相应的一条所述位线（21.1-21.3）。随机存取存储器件（20）还包括选择缓冲器（26; 46），用于当接收到选择信号时，选择选择线（27; 47）中的一个的读出。每个选择缓冲器（26; 46）包括用作驱动器的反相器（29）。逆变器（29）之后是用于限制相应选择线（27; 47）处的输出电压摆幅的二极管（30）。

8. 发明申请

WO0152265A2 DECODER CIRCUIT 审中-公开
标题翻译：解码器电路
公开(公告)号：WO0152265A2
公开(公告)日：2001-07-19
申请号：PCT/GB0100116
申请日：2001-01-12
申请人： ELEMENT 14 INC , BEAT ROBERT
发明人： BEAT ROBERT
IPC分类号： G11C8/10 , G11C11/418 , G11C11/00
CPC分类号： G11C11/418 , G11C8/10
摘要： A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.
摘要翻译：一种解码电路，用于根据多条输入线的状态选择多条输出线中的一条输出线，该电路包括：第一解码装置，包括：第一解码节点; 第一预充电电路，用于将第一解码节点充电到充电电位; 第一放电电路，其包括多个切换装置，每个切换装置都可以根据各条输入线的状态进行操作，以将第一解码节点耦合到放电电位; 以及第一选择电路，其耦合到所述输出线中的相应一者，并且可响应于第一启用信号而操作以在所述第一解码节点未放电的情况下选择所述输出线; 以及第二解码装置，包括：第二解码节点; 第二预充电电路，用于将第二解码节点充电至充电电位; 第二放电电路，其包括多个开关装置，每个开关装置都可以根据各个输入线的状态进行操作，以将第二解码节点耦合到放电电位; 以及第二选择电路，其耦合到所述输出线中的相应输出线并且可响应于第二使能信号而操作以在所述第二放电节点未放电的情况下选择所述输出线; 其中所述第一使能信号是从所述第二解码节点的电位导出的。

9. 发明申请

WO2023034370A1 SELF-REPAIR FOR SEQUENTIAL SRAM 审中-公开
公开(公告)号：WO2023034370A1
公开(公告)日：2023-03-09
申请号：PCT/US2022/042138
申请日：2022-08-31
申请人： META PLATFORMS TECHNOLOGIES, LLC
发明人： DALLARD, Edith , LIU, Huichu , MORRIS, Daniel Henry
IPC分类号： G11C7/10 , G11C11/419 , G11C11/418
摘要： In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

10. 发明申请

WO2022197534A1 COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION 审中-公开
公开(公告)号：WO2022197534A1
公开(公告)日：2022-09-22
申请号：PCT/US2022/019856
申请日：2022-03-10
申请人： QUALCOMM INCORPORATED
发明人： MIRHAJ, Seyed Arash , SRIVASTAVA, Ankit , WADHWA, Sameer , LI, Ren , MOHAN, Suren
IPC分类号： G11C11/54 , G06N3/063 , G11C7/10 , G11C11/412 , G11C11/418 , G11C11/419
摘要： A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

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