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31. 发明申请

WO2005124787A3 ELECTRICAL DEVICE HAVING A PROGRAMMABLE RESISTOR CONNECTED IN SERIES TO A PUNCH-THROUGH DIODE AND METHOD OF MANUFACTURING THEREFOR 审中-公开
公开(公告)号：WO2005124787A3
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051893
申请日：2005-06-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
摘要： The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.

32. 发明申请

WO2007052207A1 MEMORY MATRIX COMPOSED OF MEMORY CELLS EACH CONSTITUTED BY A TRANSISTOR AND A MEMORY ELEMENT CONNECTED IN PARALLEL 审中-公开
标题翻译：由晶体管构成的记忆基质的记忆矩阵和与并联连接的记忆元素
公开(公告)号：WO2007052207A1
公开(公告)日：2007-05-10
申请号：PCT/IB2006/054000
申请日：2006-10-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
发明人： VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
IPC分类号： G11C16/02 , G11C13/02 , G11C11/15 , G11C11/16
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/75 , H01L27/112 , H01L27/11206
摘要： A memory matrix (10) in an electronic circuit comprises rows and columns of cells (100), each cell comprising an access control transistor (106) and a memory circuit element (104). Each column comprises a series arrangement (102) of main current channels of a plurality of the access control transistors (106). The memory element (104) in each cell (100) is coupled in parallel to the main current channel of the access control transistor (106) of the cell (100). Word lines (14) are coupled to control electrodes of the access control transistors (106) in cells (100). During readout an addressed one of access control transistors (106) of the series arrangement (102) is switched to a non-conductive state and the remaining ones of the access control transistors (102) of said series arrangement (102) are switched to a conductive state during access to the memory cells (100). A sensing circuit (16) coupled to the series arrangements (102) for measuring conductivity of the series arrangements (102), which is determined mainly by the conductivity of the memory element (104) of the selected cell.
摘要翻译：电子电路中的存储矩阵（10）包括单元的行和列（100），每个单元包括访问控制晶体管（106）和存储器电路元件（104）。每列包括多个访问控制晶体管（106）的主电流通道的串联装置（102）。每个单元（100）中的存储元件（104）与单元（100）的访问控制晶体管（106）的主电流通道并联耦合。字线（14）耦合到单元（100）中的访问控制晶体管（106）的控制电极。在读出期间，串联装置（102）的访问控制晶体管（106）中的寻址的一个被切换到非导通状态，并且所述串联装置（102）的其余的访问控制晶体管（102）被切换到在访问存储单元（100）期间的导通状态。耦合到串联装置（102）的感测电路（16），用于测量主要由所选择的单元的存储元件（104）的电导率决定的串联装置（102）的导电性。

33. 发明申请

WO2006095278A1 DRIVING OF A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：驱动电阻滞后元件的记忆矩阵
公开(公告)号：WO2006095278A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050617
申请日：2006-02-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读取极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

34. 发明申请

WO2004042831A2 RADIATION-EMITTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：辐射发射半导体器件及其制造方法
公开(公告)号：WO2004042831A2
公开(公告)日：2004-05-21
申请号：PCT/IB2003/004881
申请日：2003-10-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WOERLEE, Pierre, H. , 'T HOOFT, Gert, W. , HOLLEMAN, Jisk
发明人： WOERLEE, Pierre, H. , 'T HOOFT, Gert, W. , HOLLEMAN, Jisk
IPC分类号： H01L33/00
CPC分类号： H01L33/34 , H01L27/15
摘要： Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the substrate (2). The lateral semiconductor diode comprises a first semiconductor region (3) of a first conductivity type and with a first doping concentration, a second semiconductor region (4) of the first or a second conductivity type opposite to the first conductivity type and with a second doping concentration which is lower than the first doping concentration, and a third semiconductor region (5) of the second conductivity type and with a third doping concentration which is higher than the second doping concentration, the first and the third region (3, 5) each being provided with a connection region (6, 8), and, during operation, radiation (S) being generated in the second region (4) due to recombination of charge carriers injected therein from the first and the third region (3, 5). According to the invention, the second semiconductor region (4) comprises a central part (4A) which is surrounded by a further part (4B) the bandgap of which is larger than the bandgap of the central part (4A). In this way, the radiation yield is increased in an indirect semiconductor material such as silicon in the central part (4A) as translation of the relatively long-living charge carriers towards a non-radiative recombination center is limited because of the barriers in the valence and conduction band in the further part (4B). Preferably, the bandgap in the further part (4B) is made larger in that the thickness of said part (4B) is so small that quantum size effects occur therein, while the central part (4A) has a thickness which is so large that such effects do not occur or substantially do not occur.
摘要翻译：辐射发射半导体器件及其制造方法。本发明涉及一种包括含硅半导体主体（1）和基板（2）的辐射发射半导体器件（10），该半导体本体（1）包括位于绝缘层（7）上的横向半导体二极管将二极管与衬底（2）分开。横向半导体二极管包括第一导电类型和第一掺杂浓度的第一半导体区域（3），与第一导电类型相反的第一或第二导电类型的第二半导体区域（4）和第二掺杂浓度低于第一掺杂浓度的浓度，以及第二导电类型的第三半导体区域（5）和高于第二掺杂浓度的第三掺杂浓度，第一和第三区域（3,5）各自设置有连接区域（6,8），并且在操作期间，由于从第一和第三区域（3,5）注入的电荷载流子的复合，在第二区域（4）中产生辐射（S）。根据本发明，第二半导体区域（4）包括由带隙大于中心部分（4A）的带隙的另一部分（4B）包围的中心部分（4A）。以这种方式，中间部分（4A）中的间接半导体材料（例如硅）的辐射产量增加，因为相对较长寿命的电荷载流子朝向非辐射复合中心的平移由于价态的障碍而受到限制和另一部分（4B）中的导带。优选地，使另一部分（4B）中的带隙变得更大，因为所述部分（4B）的厚度如此小以致其中出现量子尺寸效应，而中心部分（4A）具有如此大的厚度效果不会发生或基本不发生。

35. 发明申请

WO2007034384A3 SINGLE THRESHOLD AND SINGLE CONDUCTIVITY TYPE LOGIC 审中-公开
公开(公告)号：WO2007034384A3
公开(公告)日：2007-03-29
申请号：PCT/IB2006/053281
申请日：2006-09-14
申请人： NXP B.V. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MIJIRITSKII, Andrei , WOERLEE, Pierre, H.
发明人： VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MIJIRITSKII, Andrei , WOERLEE, Pierre, H.
IPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.

36. 发明申请

WO2007066276A2 AN ELECTRONIC CIRCUIT WITH A MEMORY MATRIX 审中-公开
标题翻译：具有存储矩阵的电子电路
公开(公告)号：WO2007066276A2
公开(公告)日：2007-06-14
申请号：PCT/IB2006/054583
申请日：2006-12-04
申请人： NXP B.V. , LAMBERT, Nicolaas , VAN ACHT, Victor, M., G. , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
发明人： LAMBERT, Nicolaas , VAN ACHT, Victor, M., G. , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有行和列存储器单元（16）的存储器矩阵（60）。第一行导体（10,12）被设置用于每一行。第二行导体（12）被设置用于连续地重叠成对的相邻行。列导体（14）为每个列提供。每个存储器单元（16）包括存取晶体管（160），节点（166）以及第一和第二电阻式存储器元件（162,164）。存取晶体管（160）最好是一个垂直晶体管，其具有耦合到存储单元（16）的行的第一行导体（10）的控制电极，耦合在用于该列的列导体（14）（160）和节点（166）之间。第一和第二电阻式存储器元件（162,164）耦合在节点（166）与第二行导体（12）之间，用于存储器单元所属的行对。

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