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1. 发明申请

WO2006051455A1 MEMORY INTEGRATED CIRCUIT 审中-公开
标题翻译：内存集成电路
公开(公告)号：WO2006051455A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053604
申请日：2005-11-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/1063 , G11C11/56
摘要： A memory integrated circuit contains a sensing circuit (12) that receives signals from addressed memory cells. The sensing circuit determines in which of a number of ranges the signals fall, the number of ranges being greater than the number values to which the cells can be programmed. An output circuit is provided that is arranged to supply either only data words that have been inferred from the detection, or also further information that provides more information about the ranges that have been detected than the data words only. Dependent on a control signal from external terminals of the memory integrated circuit the output circuit supplies the data words only to the external terminals or also the further information about the detected ranges in addition to the data words.
摘要翻译：存储器集成电路包含从寻址的存储器单元接收信号的感测电路（12）。感测电路确定信号下降的范围中的哪一个，范围的数量大于可以编程单元的数字值。提供了一种输出电路，其被布置为仅提供从检测中推断出的数据字，或者还提供了与仅数据字相比已经被检测的范围的更多信息的其他信息。取决于来自存储器集成电路的外部端子的控制信号，输出电路仅将数据字提供给外部端子，或者除了数据字之外还提供关于检测范围的进一步信息。

2. 发明申请

WO2006095278A1 DRIVING OF A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：驱动电阻滞后元件的记忆矩阵
公开(公告)号：WO2006095278A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050617
申请日：2006-02-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读取极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

3. 发明申请

WO2006095295A1 CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：具有电阻HYSTERESIS元件的记忆矩阵的控制
公开(公告)号：WO2006095295A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050672
申请日：2006-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second . During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12) , without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间来自第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）来回切换到全列更新状态在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

4. 发明申请

WO2005101207A1 DATA HANDLING DEVICE THAT CORRECTS ERRORS IN A DATA MEMORY 审中-公开
标题翻译：数据处理设备，用于校正数据存储器中的错误
公开(公告)号：WO2005101207A1
公开(公告)日：2005-10-27
申请号：PCT/IB2005/051106
申请日：2005-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G06F11/10
CPC分类号： G06F11/1008
摘要： A data handling device is provided with a data memory (10) with an address input and a data output, for outputting multi-bit words. The data memory (10) has a structure that gives rise to potential errors at correlated positions in words from a group of words. An erasure memory unit (16) stores bit position information associated with a group of the words, and outputs the bit position information when a word from the group for which bit position information is stored is addressed in the data memory (10). An error correction and detection unit (12) is arranged to correct words from the data memory (10), using error erasure for bits at bit positions selected by the bit position information from the erasure memory unit (16) for the groups to which the words belong.
摘要翻译：数据处理装置具有用于输出多位字的地址输入和数据输出的数据存储器（10）。数据存储器（10）具有在一组单词中产生相关位置上的潜在错误的结构。擦除存储器单元（16）存储与一组字相关联的位位置信息，并且当来自存储位位置信息的组中的字被寻址到数据存储器（10）中时，输出位位置信息。错误校正和检测单元（12）被布置为使用对来自擦除存储器单元（16）的位位置信息选择的比特位置处的比特的错误擦除来校正来自数据存储器（10）的单词，词属于

5. 发明申请

WO2005104132A1 ELECTRONIC CIRCUIT WITH MEMORY FOR WHICH A THRESHOLD LEVEL IS SELECTED 审中-公开
标题翻译：具有选择阈值级别的存储器的电子电路
公开(公告)号：WO2005104132A1
公开(公告)日：2005-11-03
申请号：PCT/IB2005/051305
申请日：2005-04-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

6. 发明申请

WO2005124787A3 ELECTRICAL DEVICE HAVING A PROGRAMMABLE RESISTOR CONNECTED IN SERIES TO A PUNCH-THROUGH DIODE AND METHOD OF MANUFACTURING THEREFOR 审中-公开
公开(公告)号：WO2005124787A3
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051893
申请日：2005-06-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
摘要： The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.

7. 发明申请

WO2006126110A1 ANTI-FUSE MEMORY DEVICE 审中-公开
标题翻译：防静电存储器件
公开(公告)号：WO2006126110A1
公开(公告)日：2006-11-30
申请号：PCT/IB2006/051406
申请日：2006-05-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DER SLUIS, Paul , MIJIRITSKII, Andrei , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas
发明人： VAN DER SLUIS, Paul , MIJIRITSKII, Andrei , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas
IPC分类号： G11C17/16 , H01L23/525
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.
摘要翻译：一次性可编程（OTP）存储器单元（10），包括涂覆有第二导电稳定过渡化合物（14）的第一金属层（12），其间具有绝缘层（16）。第一层和第二层（12,14）根据它们之间的吉布斯自由能的差异来选择，这决定了由于两种材料之间的放热化学反应而产生的化学能。第一层和第二层（12,14）的材料本身是高度热稳定的，但是当向单元（10）施加电压时，导致绝缘层（16）的局部击穿产生热点（18 ），其在第一和第二层（12,14）之间引起放热化学反应。放热反应产生足够的热量（20）以在电池上产生短路并因此降低其电阻。

8. 发明申请

WO2006075262A1 CIRCUIT WITH A MEMORY ARRAY AND A REFERENCE LEVEL GENERATOR CIRCUIT 审中-公开
标题翻译：具有存储器阵列的电路和参考电平发生器电路
公开(公告)号：WO2006075262A1
公开(公告)日：2006-07-20
申请号：PCT/IB2006/050037
申请日：2006-01-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H.
发明人： VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H.
IPC分类号： G11C7/06
CPC分类号： G11C7/14
摘要： A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi- level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.
摘要翻译：电路包括存储器单元阵列（10）。多个感测电路（20）耦合到相应存储单元（10）的输出（14），用于将存储单元（10）中的相应一个的输出信号与参考信号进行比较以形成数据信号来自存储单元（10）中的相应一个的输出信号。参考发生器电路（24,26）从一个和形成参考信号，其中寻址组的每个存储单元（10）中的每个相应的一个贡献作为存储单元的相应一个的输出信号的函数（10）。在超过参考信号的饱和距离上的输出信号值的贡献相等，并且在超过参考信号以下的饱和距离处的输出信号值的贡献相等。在单元格中存储多级数据的情况下，从基准电平以上和低于基准电平的中心电平到饱和电平的距离是相互不同的，其比例对应于已编程的单元计数的比率各级别。

9. 发明申请

WO2007052207A1 MEMORY MATRIX COMPOSED OF MEMORY CELLS EACH CONSTITUTED BY A TRANSISTOR AND A MEMORY ELEMENT CONNECTED IN PARALLEL 审中-公开
标题翻译：由晶体管构成的记忆基质的记忆矩阵和与并联连接的记忆元素
公开(公告)号：WO2007052207A1
公开(公告)日：2007-05-10
申请号：PCT/IB2006/054000
申请日：2006-10-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
发明人： VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , MIJIRITSKII, Andrei
IPC分类号： G11C16/02 , G11C13/02 , G11C11/15 , G11C11/16
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/75 , H01L27/112 , H01L27/11206
摘要： A memory matrix (10) in an electronic circuit comprises rows and columns of cells (100), each cell comprising an access control transistor (106) and a memory circuit element (104). Each column comprises a series arrangement (102) of main current channels of a plurality of the access control transistors (106). The memory element (104) in each cell (100) is coupled in parallel to the main current channel of the access control transistor (106) of the cell (100). Word lines (14) are coupled to control electrodes of the access control transistors (106) in cells (100). During readout an addressed one of access control transistors (106) of the series arrangement (102) is switched to a non-conductive state and the remaining ones of the access control transistors (102) of said series arrangement (102) are switched to a conductive state during access to the memory cells (100). A sensing circuit (16) coupled to the series arrangements (102) for measuring conductivity of the series arrangements (102), which is determined mainly by the conductivity of the memory element (104) of the selected cell.
摘要翻译：电子电路中的存储矩阵（10）包括单元的行和列（100），每个单元包括访问控制晶体管（106）和存储器电路元件（104）。每列包括多个访问控制晶体管（106）的主电流通道的串联装置（102）。每个单元（100）中的存储元件（104）与单元（100）的访问控制晶体管（106）的主电流通道并联耦合。字线（14）耦合到单元（100）中的访问控制晶体管（106）的控制电极。在读出期间，串联装置（102）的访问控制晶体管（106）中的寻址的一个被切换到非导通状态，并且所述串联装置（102）的其余的访问控制晶体管（102）被切换到在访问存储单元（100）期间的导通状态。耦合到串联装置（102）的感测电路（16），用于测量主要由所选择的单元的存储元件（104）的电导率决定的串联装置（102）的导电性。

10. 发明申请

WO2007042970A1 SINGLE THRESHOLD AND SINGLE CONDUCTIVITY TYPE AMPLIFIER/BUFFER 审中-公开
标题翻译：单路和单电导型放大器/缓冲器
公开(公告)号：WO2007042970A1
公开(公告)日：2007-04-19
申请号：PCT/IB2006/053633
申请日：2006-10-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MIJIRITSKII, Andrei , WOERLEE, Pierre, H.
发明人： VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MIJIRITSKII, Andrei , WOERLEE, Pierre, H.
IPC分类号： H03K17/06 , H03K19/0944
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

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