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21. 发明申请

WO2003036716A1 MULTI-STAGE, HIGH FREQUENCY, HIGH POWER SIGNAL AMPLIFIER 审中-公开
标题翻译：多级，高频，大功率信号放大器
公开(公告)号：WO2003036716A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033899
申请日：2002-10-21
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , MOLLER, Thomas, W. , LEIGHTON, Larry , PERUGUPALLI, Prasanth
发明人： MOLLER, Thomas, W. , LEIGHTON, Larry , PERUGUPALLI, Prasanth
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/48 , H01L23/66 , H01L24/48 , H01L2223/6644 , H01L2223/665 , H01L2224/32188 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01068 , H01L2924/01072 , H01L2924/1306 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H03F3/604 , H01L2924/00 , H01L2224/45099
摘要： A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner emplemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal. A plurality of corresponding output matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple the respective component output signals at the transistor outputs to an output impedance.
摘要翻译：宽带RF信号放大器包括附接到基座的表面的多个晶体管，每个晶体管具有输入和输出。电连接到晶体管输入的RF输入路径包括实现在多层印刷电路板中并被配置为将RF输入信号分成多个分量输入信号的无源分离器。包括在印刷电路板中实现的四分之一波长传输线的多个对应的输入匹配网络将各个分量输入信号以输入阻抗耦合到晶体管输入，输入匹配网络还包括附接到基座的相应的输入匹配电容器。电连接到晶体管输出的RF输出路径包括在印刷电路板中实现的被配置为将在晶体管输出处接收的分量输出信号组合成RF输出信号的无源组合器。包括在印刷电路板中实施的四分之一波长传输线的多个对应的输出匹配网络将晶体管输出端处的各个分量输出信号耦合到输出阻抗。

22. 发明申请

WO2002078086A2 POWER TRANSISTOR PACKAGE WITH INTEGRATED FLANGE FOR SURFACE MOUNT HEAT REMOVAL 审中-公开
标题翻译：带集成法兰的功率晶体管封装，用于表面安装热量去除
公开(公告)号：WO2002078086A2
公开(公告)日：2002-10-03
申请号：PCT/US2002/010562
申请日：2002-03-26
申请人： ERICSSON INC.
发明人： LAUREANTI, Steven, J.
IPC分类号： H01L23/367
CPC分类号： H01L23/49844 , H01L23/3677 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/19107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A transistor package comprises a first layer in which a thermally conductive flange is integrated into a dielectric substrate layer, a transistor attached to the flange, and input and output contacts coupled to the transistor. The transistor package is attached to a circuit board such that its input and output contacts are electrically coupled to associated conductors on the circuit board. In one embodiment, the transistor package further comprises additional dielectric layers, bonded to the bottom layer, in which a top layer forms a lid covering the transistor. The layers intermediate the bottom and top layers have central areas cut away where the layers overlap the transistor, thereby forming an interior chamber in the package. Impedance matching networks may also be provided to couple the transistor input and output terminals to their respective contacts, where the matching networks tune the input and output impedances of the package. These matching networks may comprise a plurality of components and conductors implemented the intermediate layers and/or the top layer.
摘要翻译：晶体管封装包括第一层，其中导热凸缘集成到电介质基底层中，连接到凸缘的晶体管，以及耦合到晶体管的输入和输出触点。晶体管封装被附接到电路板，使得其输入和输出触点电耦合到电路板上的相关导体。在一个实施例中，晶体管封装还包括结合到底层的附加电介质层，其中顶层形成覆盖晶体管的盖。在顶层和中间层之间的层中间区域被切掉，其中层与晶体管重叠，从而在封装中形成内部室。还可以提供阻抗匹配网络以将晶体管输入和输出端子耦合到它们各自的触点，其中匹配网络调谐封装的输入和输出阻抗。这些匹配网络可以包括实现中间层和/或顶层的多个部件和导体。

23. 发明申请

WO01046991A3 METHOD AND APPARATUS FOR PACKAGING HIGH FREQUENCY COMPONENTS 审中-公开
标题翻译：包装高频部件的方法和装置
公开(公告)号：WO01046991A3
公开(公告)日：2002-02-21
申请号：PCT/US2000/042788
申请日：2000-12-12
IPC分类号： G02B6/42 , H01S5/022 , H01S5/042 , H01S5/062 , H01S5/14 , H01S5/183 , H04B10/158 , H05K9/00 , H01L31/0203
CPC分类号： H01S5/02284 , G02B6/4203 , H01L2224/48137 , H01L2224/49171 , H01L2924/1305 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H01S5/02216 , H01S5/02244 , H01S5/02248 , H01S5/0427 , H01S5/06226 , H01S5/183 , H01L2924/00
摘要： The invention provides a method and apparatus for packaging high frequency electrical and/or electro-optical components. The package (140) may be surface mounted on a board with other electrical components. The shielding provided by the package minimizes electromagnetic interference with other electrical components on the board. The package includes a controlled impedance I/O interface for coupling with the electrical or electro-optical components in the package. The interface may also include a differential I/O capability to further control electromagnetic fields generated at the interface. Additionally, the package may include an optical link provided by one or more optical fibers (150) extending from the package. These features allow the package to be used for a variety of high frequency components including optical transmitters (254) and optical receivers. A method for fabricating the package is also disclosed. The package may be fabricated with relatively low cost and a reduced form factor as compared with prior art packages.
摘要翻译：本发明提供了一种用于封装高频电和/或电光部件的方法和装置。封装（140）可以表面安装在具有其它电气部件的板上。封装提供的屏蔽最大程度地减少电路板上其他电气元件的电磁干扰。该封装包括用于与封装中的电气或电光部件耦合的受控阻抗I / O接口。接口还可以包括差分I / O能力，以进一步控制在接口处产生的电磁场。另外，封装可以包括由从封装延伸的一个或多个光纤（150）提供的光学链路。这些特征允许封装用于各种高频部件，包括光发射器（254）和光接收器。还公开了一种制造封装的方法。与现有技术的封装相比，封装可以以相对较低的成本和减小的外形尺寸来制造。

24. 发明申请

WO0156083A2 MULTIPLE GROUND SIGNAL PATH LDMOS POWER PACKAGE 审中-公开
标题翻译：多功能地面信号路径LDMOS电源封装
公开(公告)号：WO0156083A2
公开(公告)日：2001-08-02
申请号：PCT/US0101572
申请日：2001-01-16
申请人： ERICSSON INC
发明人： LEIGHTON LARRY , MOLLER THOMAS , AHL BENGT , HOYER HENRIK
IPC分类号： H01L23/12 , H01L23/498 , H01L23/66
CPC分类号： H01L23/49861 , H01L23/49827 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An LDMOS power package includes a conductive mounting flange, with a dielectric window substrate attached to the mounting flange exposing a portion of the mounting flange. A semiconductor die is attached to the exposed portion of the mounting flange, the die having a plurality of transistors formed thereon, the transistors having respective input (gate) terminals, output (drain) terminals and a ground (source) terminal, the ground terminal electrically coupled to the mounting flange. Respective input and output lead frames are attached to the window substrate and electrically coupled to the respective transistor input and output terminals. A ground lead frame is also attached to the substrate and electrically coupled to the mounting flange via a conductive path, wherein the respective input, output and ground lead frames are electrically isolated from one another. The conductive path may comprise one or more metallic layers extending along the outer and/or inner surface of the window substrate. The conductive path may alternatively, or additionally comprise a plurality of vias extending through the window substrate.
摘要翻译： LDMOS功率封装包括导电安装凸缘，其中介电窗口基板附接到安装凸缘，露出安装凸缘的一部分。半导体管芯安装在安装法兰的暴露部分，管芯上形成有多个晶体管，晶体管具有各自的输入（栅极）端子，输出（漏极）端子和接地（源极）端子，接地端子电耦合到安装凸缘。各个输入和输出引线框架附接到窗口基板并电耦合到相应的晶体管输入和输出端子。接地引线框架也附接到基板并且经由导电路径电耦合到安装凸缘，其中相应的输入，输出和接地引线框架彼此电隔离。导电路径可以包括沿着窗户基板的外表面和/或内表面延伸的一个或多个金属层。导电路径可以替代地或另外包括延伸穿过窗口基板的多个通孔。

25. 发明申请

WO01050531A1 INTERCONNECTION DEVICE AND METHOD 审中-公开
标题翻译：互连装置和方法
公开(公告)号：WO01050531A1
公开(公告)日：2001-07-12
申请号：PCT/US2000/034805
申请日：2000-12-20
IPC分类号： H01L23/12 , H01L23/66
CPC分类号： H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/05599 , H01L2224/32225 , H01L2224/45014 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1423 , H01L2924/15313 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An RF microcircuit package and interconnection device is disclosed which minimizes impedance mismatch between circuit elements. Multiple signal vie and close proximity ground vies as well as tuned wire bonds are disclosed.
摘要翻译：公开了RF电路封装和互连装置，其最小化电路元件之间的阻抗失配。公开了多信号和近距离接地以及调谐线接合。

26. 发明申请

WO00038232A1 WIRE BOND COMPENSATION 审中-公开
标题翻译：电线补偿
公开(公告)号：WO00038232A1
公开(公告)日：2000-06-29
申请号：PCT/SE1999/002412
申请日：1999-12-17
IPC分类号： H01L23/66 , H05K3/32 , H05K3/40
CPC分类号： H01L24/49 , H01L23/66 , H01L24/45 , H01L24/48 , H01L2223/6611 , H01L2224/45014 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01058 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1423 , H01L2924/15153 , H01L2924/1517 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H05K3/328 , H05K3/4015 , H01L2924/00 , H01L2224/05599
摘要： A hybrid circuit and a process for the manufacturing of a hybrid circuit (11) have been provided, the circuit comprising a component (2) such as a monolithic integrated circuit, MIC, and a substrate (1), being arranged on a common carrier plate (6), the substrate and component having respective terminals (3, 3', 4, 4', 4''). The hybrid circuit furthermore comprises a pad (7, 7', 7'', 12, 13) mounted on the substrate terminal (3, 3'), whereby the pad is extending over the edge of the substrate terminal and facing the terminal (4, 4', 4'') of the component, and at least one bonding element (8, 8', 8'') or other connecting element being provided between the terminal (4) of the component and the pad (7, 7', 7'', 12, 13). The connection according to the invention provides for a very low impedance value, which can be produced accurately, reliably and economically.
摘要翻译：已经提供了混合电路和用于制造混合电路（11）的方法，该电路包括诸如单片集成电路（MIC）和基板（1）的部件（2），其布置在公共载体板（6），基板和具有各自端子（3,3'，4,4'，4“）的部件。混合电路还包括安装在基板端子（3,3'）上的焊盘（7,7'，7“，12”），由此焊盘在基板端子的边缘上延伸并面向端子 4“，4”，4“），并且至少一个接合元件（8,8'，8”）或其他连接元件设置在部件的端子（4）和垫（7， 7'，7“，12,13）。根据本发明的连接提供了非常低的阻抗值，其可以准确，可靠和经济地产生。

27. 发明申请

WO9934443A9 CERAMIC MICROELECTRONICS PACKAGE WITH CO-PLANAR WAVEGUIDE FEED-THROUGH 审中-公开
标题翻译：陶瓷微电子封装与平面波导进料
公开(公告)号：WO9934443A9
公开(公告)日：2000-03-02
申请号：PCT/US9826263
申请日：1998-12-10
申请人： STRATEDGE CORP
发明人： GOING TIMOTHY J , LINDNER ALAN W
IPC分类号： H01L23/66
CPC分类号： H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ceramic microelectronic package (200) suitable for housing high-frequency electronic devices, and a process for making such a package, are disclosed herein. The package includes a base (102), a ceramic circuit substrate (106) attached to a top surface of the base and having a first cavity for receiving a high-frequency electronic device (116), and conductive patterns (202) deposited on a surface of the circuit substrate. The patterns (204) include signal patterns and flanking ground patterns forming at least a portion of co-planar waveguide (CPW) transmission lines. Each signal pattern is preferably a signal trace, and each ground pattern may be a ground trace or plane. The ground patterns may each have a portion exposed outside the package for external connection to electrical ground. Alternately, the ground patterns may be internally connected to a ground plane formed by the base, when the base is at least partially conductive, by conductive via openings or bonding wires passing through ears cut into a perimeter of the circuit substrate. The base may also be non-conductive such that the transmission line is a suspended CPW transmission line. The package may include a ceramic seal ring (110) substrate attached to the circuit substrate and having a second cavity larger than the first cavity, and a ceramic lid (114) attached thereto such that the transmission line forms a CPW, embedded CPW, and CPW transmission line. Alternatively, the package may include a dielectric sealing cap attached to the circuit substrate and having a chamber larger than the first cavity such that the line again forms a CPW, embedded CPW, and CPW transmission line.
摘要翻译：本文公开了一种适用于容纳高频电子器件的陶瓷微电子封装（200）及其制造方法。所述封装包括基座（102），陶瓷电路基板（106），所述陶瓷电路基板（106）附接到所述基座的顶表面并具有用于接收高频电子器件（116）的第一腔，以及沉积在所述基座电路基板的表面。图案（204）包括形成共面波导（CPW）传输线的至少一部分的信号图案和侧面接地图案。每个信号图案优选地是信号迹线，并且每个接地图案可以是接地迹线或平面。接地图可以各自具有暴露在封装外部的部分，用于外部连接到电气接地。或者，当基底至少部分导电时，接地图案可以内部连接到由基底形成的接地平面，通过导电通孔开口或穿过切入电路基板的周边的耳朵的接合线。基座也可以是非导通的，使得传输线是悬挂的CPW传输线。封装可以包括附接到电路基板并且具有大于第一空腔的第二空腔的陶瓷密封环（110）和附接到其上的陶瓷盖（114），使得传输线形成CPW，嵌入式CPW，以及 CPW传输线。替代地，封装可以包括附接到电路基板并具有大于第一空腔的室的电介质密封盖，使得线再次形成CPW，嵌入式CPW和CPW传输线。

28. 发明申请

WO1984001470A1 LEADLESS CHIP CARRIER FOR LOGIC COMPONENTS 审中-公开
标题翻译：用于逻辑组件的无铅芯片载体
公开(公告)号：WO1984001470A1
公开(公告)日：1984-04-12
申请号：PCT/US1983001516
申请日：1983-09-29
申请人： MAYO FOUNDATION
发明人： MAYO FOUNDATION , GILBERT, Barry, K. , SCHWAB, Daniel, J.
IPC分类号： H01L23/02
CPC分类号： H01L23/49805 , H01L23/057 , H01L23/49822 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/45014 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/12033 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15313 , H01L2924/1532 , H01L2924/16195 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/0237 , H05K3/3442 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A carrier apparatus (40) for mounting logic components on the surface of a circuit board (41). The carrier apparatus (40) includes a housing structure defining top and bottom surfaces and further defining a cavity (50) in the bottom surface for receipt of a logic component (51). A recessed cover portion (56) is attached to the housing so as to enclose the cavity (50) thereby effectively sealing the logic component (51) in the housing. The carrier apparatus (40) includes means for mounting the housing on a circuit board such that the cover (56) does not make contact with the surface of the circuit board (41). The housing further includes means for electrically interconnecting the logic component (51) to the circuit board (41). In yet another embodiment, a carrier apparatus (100) for mounting logic components on the surface of a circuit board (41) is disclosed which utilize ground and voltage planes together with alternating signal (118) and AC ground (121) traces so as to effectuate coplanar/strip-line and coplanar/microstrip transmission line environments along portions of the signal traces (118). Consequently, this results in signal lines having a controlled impedance environment and minimized crosstalk between neighboring signal leads lying in the same plane.
摘要翻译：一种用于在电路板（41）的表面上安装逻辑部件的载体装置（40）。载体装置（40）包括限定顶表面和底表面的壳体结构，并且还在底表面中限定用于接收逻辑部件（51）的空腔（50）。凹入的盖部分（56）附接到壳体以封闭空腔（50），从而有效地密封壳体中的逻辑部件（51）。载体装置（40）包括用于将壳体安装在电路板上的装置，使得盖（56）不与电路板（41）的表面接触。壳体还包括用于将逻辑部件（51）电连接到电路板（41）的装置。在另一个实施例中，公开了一种用于在电路板（41）的表面上安装逻辑部件的载体装置（100），其利用地面和电压平面以及交流信号（118）和AC地线（121）迹线，以便沿着信号迹线（118）的部分实现共面/带状线和共平面/微带传输线环境。因此，这导致具有受控阻抗环境的信号线和位于同一平面中的相邻信号引线之间的最小串扰。

29. 发明申请

WO2015000597A9 MIXED IMPEDANCE BOND WIRE CONNECTIONS AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：混合阻抗连接线连接及其制造方法
公开(公告)号：WO2015000597A9
公开(公告)日：2015-03-26
申请号：PCT/EP2014001826
申请日：2014-07-02
申请人： ROSENBERGER HOCHFREQUENZTECH
发明人： CAHILL SEAN S , SANJUAN ERIC A
IPC分类号： H01L23/40 , H01L23/50 , H01L23/66
CPC分类号： H01L23/4952 , H01L23/49861 , H01L23/50 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2223/6611 , H01L2224/45015 , H01L2224/45565 , H01L2224/4569 , H01L2224/48011 , H01L2224/48227 , H01L2224/48247 , H01L2224/4903 , H01L2224/8501 , H01L2224/85444 , H01L2224/8592 , H01L2224/8593 , H01L2224/85931 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/30111 , H01L2924/20751 , H01L2924/20752 , H01L2224/45099 , H01L2924/00
摘要： A die package having mixed impedance leads where a first lead has a first metal core (130), and a dielectric layer surrounding the first metal core (130), and a second lead has a second metal core, and a second dielectric layer (132) surrounding the second metal core, with the dielectric thicknesses differing from each other. A method of making a die package having leads with different impedances formed by cleaning die substrate connection pads (162), connecting the die package to the die substrate connection pads via a first wirebond having a first diameter metal core (164), depositing at least one layer of dielectric on the wirebond metal core (170), metalizing the at least one layer of dielectric (174), connecting the die package to the die substrate connection pads via a second wirebond having a second diameter metal core, depositing at least one layer of dielectric on the second wirebond second diameter metal core, and metalizing the at least one layer of dielectric on the second diameter metal core, such that the first wirebond has a different impedance than the second wirebond.
摘要翻译：一种具有混合阻抗导线的管芯封装，其中第一引线具有第一金属芯（130）和围绕第一金属芯（130）的介电层，第二引线具有第二金属芯和第二电介质层（132））围绕第二金属芯，其电介质厚度彼此不同。一种制造具有通过清洁管芯衬底连接焊盘（162）形成的具有不同阻抗的引线的管芯封装的方法，通过具有第一直径金属芯（164）的第一引线键将管芯封装连接到管芯衬底连接焊盘，至少沉积在引线键合金属芯（170）上的一层电介质，使至少一层电介质（174）金属化，通过具有第二直径金属芯的第二引线键将管芯封装连接到管芯衬底连接焊盘，沉积至少一个在所述第二引线键合第二直径金属芯上的电介质层，以及使所述第二直径金属芯上的所述至少一层电介质金属化，使得所述第一引线键具有与所述第二引线键不同的阻抗。

30. 发明申请

WO2014155974A1 半導体デバイス审中-公开
标题翻译：半导体器件
公开(公告)号：WO2014155974A1
公开(公告)日：2014-10-02
申请号：PCT/JP2014/001105
申请日：2014-02-28
申请人：パナソニック株式会社
发明人：夘野　高史 , 八幡　和宏
IPC分类号： H01L23/12 , H01L23/02 , H01L23/04 , H01P5/08
CPC分类号： H05K1/0237 , H01L23/043 , H01L23/047 , H01L23/66 , H01L2223/6611 , H01L2223/6655 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/49175 , H01L2225/06548 , H01L2924/3011 , H01L2924/30111 , H05K1/18 , H05K2201/10166 , H05K2201/10689 , H01L2924/00014 , H01L2924/00 , H01L2224/49111
摘要：安価に製造でき、高周波特性のバラツキが抑制された半導体デバイスを提供する。内部整合回路基板（１０７，１０８）が、入力端子（１０２）と半導体素子（１０６）との間の入力側の信号伝送経路、および半導体素子と出力端子（１０３）との間の出力側の信号伝送経路の少なくとも一方の信号伝送経路に配置され、入力端子に接続される外部回路の出力インピーダンスと半導体デバイスの入力インピーダンス、または出力端子に接続される外部回路の入力インピーダンスと半導体デバイスの出力インピーダンスの少なくとも一方を整合させるために設けられ、ワイヤ長が変化すると半導体デバイスの高周波特性が許容値を超えて変化する少なくとも１つのワイヤ（１１１）により電気的に接続される部品同士を接触した状態でパッケージ内部に配置している。
摘要翻译：本发明的目的是提供一种可以以低成本制造并且抑制高频特性的不均匀性的半导体器件。内部匹配电路板（107,108）设置在输入端（102）和半导体元件（106）之间的输入侧的信号传输路径和输出侧的信号传输路径中的至少一个之间，半导体元件和输出端子（103），并且被设置为执行与输入端子连接的外部电路的输出阻抗和半导体器件的输入阻抗之间的匹配，和/或连接的外部电路的输入阻抗到半导体器件的输出端子和输出阻抗。通过至少一根导线（111）电连接在一起的部件，其中半导体器件的高频特性在电线长度变化时改变为超过阈值，被布置在封装的内部彼此接触的状态。

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