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21. 发明申请

WO0250899A3 SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装
公开(公告)号：WO0250899A3
公开(公告)日：2003-04-24
申请号：PCT/GB0105674
申请日：2001-12-19
申请人： CONVERGENCE TECHNOLOGIES LTD , SIU WING MING , PIESOLD ALEXANDER JAMES
发明人： SIU WING MING
IPC分类号： H01L25/065 , H01L25/10 , H01L23/16 , H01L23/498
CPC分类号： H01L25/0652 , H01L25/105 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/01087 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor package includes a metallic foil (10) having a front surface and a rear surface, which foil (10) is formed to have a recess portion (12) including a bottom and an extended border region (14) around the recess portion (12). A substrate (30) is attached to the front surface of the foil (10) over the border region (14) to provide a support for electrical connection of a semiconductor element (40). The substrate (30) has an opening exposing the recess portion (12). A stiffener (20) is formed on the rear surface of the foil (10) for anhancing the rigidity of the foil (10). The stiffener (20) extends over the border region (14) and around the recess portion (12) exposed for heat dissipation. A semiconductor element (40) is mounted on the bottom of and within the recess portion (12).
摘要翻译：半导体封装包括具有前表面和后表面的金属箔（10），该箔（10）形成为具有包括底部的凹部（12）和围绕凹部的延伸边界区域（14） 12）。衬底（30）在边界区域（14）上连接到箔（10）的前表面以提供用于半导体元件（40）的电连接的支撑。基板（30）具有露出凹部（12）的开口。在箔（10）的后表面上形成加强件（20），以增强箔（10）的刚性。加强件（20）在边界区域（14）上延伸并且围绕露出的用于散热的凹部（12）延伸。半导体元件（40）安装在凹部（12）的底部和内部。

22. 发明申请

WO2002089540A1 プリント回路板、その製造方法及びＣＳＰの製造方法审中-公开
标题翻译：印刷电路板及其制造方法和CSP制造METHDO
公开(公告)号：WO2002089540A1
公开(公告)日：2002-11-07
申请号：PCT/JP2002/004016
申请日：2002-04-23
申请人：三井金属鉱業株式会社 , 一柳彰 , 林克彦 , 片岡龍男 , 河村裕和 , 石井正人
发明人：一柳彰 , 林克彦 , 片岡龍男 , 河村裕和 , 石井正人
IPC分类号： H05K1/11
CPC分类号： H01L25/50 , H01L21/486 , H01L23/49816 , H01L23/49827 , H01L25/0657 , H01L2224/16 , H01L2224/16225 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/005 , H05K3/4046 , H05K3/4614 , H05K3/4617 , H05K2201/10416 , H05K2203/033 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , H01L2224/0401
摘要： A printed circuit board comprising an insulating substrate, a through-hole formed in the insulating substrate, an implant material filling the through-hole, and a wiring pattern formed on both faces of the insulating substrate and electrically connected with the implant material, characterized in that one face of a conductor wiring layer wherein a bump penetrates from one face to the other face and protrudes is adhered to the insulating substrate so as to be electrically connected to the implant material. This bump conductor wiring layer of this printed circuit board has a large degree of freedom in forming a wiring pattern, through-hole, and bump and is unlike conventional handled separately from the insulating substrate. Therefore, the effect arises that this circuit board is the target of commercial trading by itself.
摘要翻译：一种印刷电路板，包括绝缘基板，形成在所述绝缘基板中的通孔，填充所述通孔的注入材料以及形成在所述绝缘基板的两个表面上并与所述植入材料电连接的布线图案，其特征在于，其中凸块从一个面渗透到另一个表面并突出的导体布线层的一个表面粘附到绝缘基板上，从而与植入材料电连接。该印刷电路板的凸点导体布线层在形成布线图案，通孔和凸块方面具有很大的自由度，并且与绝缘基板分开地传统处理不同。因此，这种电路板本身就是商业交易的目标。

23. 发明申请

WO02029890A2 SEMICONDUCTOR STACKED DIE DEVICES AND METHODS OF FORMING SEMICONDUCTOR STACKED DIE DEVICES 审中-公开
标题翻译：半导体堆叠电路器件及形成半导体堆叠电路器件的方法
公开(公告)号：WO02029890A2
公开(公告)日：2002-04-11
申请号：PCT/US2001/029578
申请日：2001-09-19
IPC分类号： H01L21/98 , H01L25/065 , H01L23/00
CPC分类号： H01L25/50 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming semiconductor devices are described. In one embodiment, at least one conductive structure is formed within a plurality of semiconductor substrate. At least portions of one of the conductive structures have oppositely facing, exposed outer surfaces. Individual substrates are stacked together in a die stack such that individual conductive structures on each substrate are in electrical contact with the conductive structures on a next adjacent substrate. In a preferred embodiment, the conductive structures comprise multi-layered, conductive pad structures.
摘要翻译：描述了半导体器件和半导体器件形成方法。在一个实施例中，在多个半导体衬底内形成至少一个导电结构。一个导电结构的至少一部分具有相对面对的暴露的外表面。单个衬底在管芯堆叠中堆叠在一起，使得每个衬底上的各个导电结构与下一个相邻衬底上的导电结构电接触。在优选实施例中，导电结构包括多层导电垫结构。

24. 发明申请

WO01099187A1 PANEL STACKING OF BGA DEVICES TO FORM THREE-DIMENSIONAL MODULES 审中-公开
标题翻译： BGA器件的面板堆叠形成三维模块
公开(公告)号：WO01099187A1
公开(公告)日：2001-12-27
申请号：PCT/US2001/010130
申请日：2001-03-29
IPC分类号： H01L25/065 , H05K1/14 , H05K3/34 , H05K3/36 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/141 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H05K1/144 , H05K3/3436 , H05K3/368 , H05K2201/10378 , H05K2201/10515 , H05K2201/10674 , H05K2201/2018
摘要： A chip stack (10) comprising at least two base layers (12), each of which includes a base substrate (14) and a first conductive pattern disposed on the base substrate (14). The chip stack (10) further comprises at least one interconnect frame (34) having a second conductive pattern disposed thereon. The interconnect frame (34) is disposed between the base layers (12), with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers (12). Also included in the chip stack (10) are at least two integrated circuit chips (70) which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips (70) is at least partially circumvented by the interconnect frame (34) and at least partially covered by one of the base layers (12). The chip stack (10) further comprises a transposer layer (52) comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers (1 2) is electrically connected to the third conductive pattern of the transposer layer (52).
摘要翻译：一种包括至少两个基层（12）的芯片堆叠（10），每个基层包括基底基板（14）和设置在基底基板（14）上的第一导电图案。芯片堆叠（10）还包括至少一个布置在其上的第二导电图案的互连框架（34）。互连框架（34）设置在基底层（12）之间，第二导电图形电连接到每个基底层（12）的第一导电图案。还包括在芯片堆叠（10）中的至少两个集成电路芯片（70），其电连接到相应的第一导电图案。集成电路芯片（70）中的一个至少部分地由互连框架（34）绕过并且至少部分地被基底层（12）之一覆盖。芯片堆叠（10）还包括转置器层（52），其包括其上布置有第三导电图案的转印器基板。基底层（12）之一的第一导电图形电连接到转印层（52）的第三导电图案。

25. 发明申请

WO00064229A1 CONTACT MODULE, AS FOR A SMART CARD, AND METHOD FOR MAKING SAME 审中-公开
标题翻译：联系模块，用于智能卡，以及制造它的方法
公开(公告)号：WO00064229A1
公开(公告)日：2000-10-26
申请号：PCT/US2000/009144
申请日：2000-04-06
IPC分类号： B32B3/08 , B32B7/12 , B32B33/00 , B32B37/20 , G06K19/077 , H01L23/055 , H01L23/498 , H01L23/538 , H01Q1/22 , H01Q1/36 , H01Q1/38 , H01Q7/00 , H01Q23/00 , H05K1/00 , H05K1/11 , H05K1/16 , H05K3/40 , H05K3/42 , H05K7/02 , H05K3/30
CPC分类号： B32B37/203 , B32B3/08 , B32B7/12 , B32B33/00 , B32B2425/00 , B32B2429/00 , B32B2519/02 , G06K19/07743 , G06K19/07745 , G06K19/07747 , H01L23/055 , H01L23/49838 , H01L23/4985 , H01L23/49855 , H01L23/5387 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01021 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/22 , H01Q1/2225 , H01Q1/36 , H01Q1/38 , H01Q7/00 , H01Q7/005 , H01Q23/00 , H05K1/0393 , H05K1/113 , H05K1/165 , H05K3/4069 , H05K3/423 , H05K2201/0355 , H05K2201/0394 , H05K2201/10674 , H05K2203/1453 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/013
摘要： A module (100), such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprises a pattern of metal contacts (114a, 114b) having a first and a second surface and electrically conductive vias (132a, 132b) built up on the first surface of the metal contacts (114a, 114b). A layer of dielectric adhesive (120) on the first surface of the pattern of metal contacts (114a, 114b) surrounds the electrically conductive vias (132a, 132b) except the ends open (134a, 134b) thereof distal from the metal contacts (114a, 114b). An electronic device (140) has electrical contacts (142a, 142b) connected to the exposed ends (134a, 134b) of the conductive vias (132a, 132b), as by wire bonds or by flip-chip type connections (144).
摘要翻译：诸如用于将电子设备嵌入到信用卡，智能卡，识别标签或其它物品中的接触模块的模块（100）包括具有第一和第二表面以及电气的金属触点（114a，114b）的图案在金属触点（114a，114b）的第一表面上形成的导电通孔（132a，132b）。在金属触点（114a，114b）的图案的第一表面上的电介质粘合剂层（120）围绕导电通孔（132a，132b），除了远离金属触点（114a）的端部打开（134a，134b），114b）。电子设备（140）具有通过引线接合或倒装芯片型连接（144）连接到导电通孔（132a，132b）的暴露端（134a，134b）的电触点（142a，142b）。

26. 发明申请

WO00014802A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF, CIRCUIT BOARD, AND ELECTRONIC DEVICE 审中-公开
标题翻译：半导体器件，其制造方法，电路板和电子器件
公开(公告)号：WO00014802A1
公开(公告)日：2000-03-16
申请号：PCT/JP1999/004785
申请日：1999-09-03
IPC分类号： H01L21/56 , H01L23/498 , H01L23/538 , H01L25/065 , H01L23/32
CPC分类号： H01L23/5385 , H01L21/563 , H01L23/49816 , H01L23/5387 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05569 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2225/06517 , H01L2225/06575 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/15311 , H01L2924/00 , H01L2224/05599 , H01L2224/05144 , H01L2224/05155
摘要： A semiconductor device comprises a plurality of semiconductor elements (20, 30) having electrodes (22, 32) and arranged in the same plane; a substrate (10) having wiring patterns (12) including bonding parts (14) connected with the electrodes (22, 32) of the semiconductor elements (20, 30) and lands (16) connected with the bonding parts (14); and external electrodes (40) provided on the land and connected with the electrodes (22, 32) through the wiring patterns (12).
摘要翻译：一种半导体器件包括具有电极（22,32）并布置在同一平面上的多个半导体元件（20,30）具有布线图案（12）的基板（10），包括与半导体元件（20,30）的电极（22,32）连接的接合部（14）和与接合部（14）连接的接合区（16）。和外部电极（40），其设置在焊盘上并通过布线图案（12）与电极（22,32）连接。

27. 发明申请

WO1996003020A1 INTEGRALLY BUMPED ELECTRONIC PACKAGE COMPONENTS 审中-公开
标题翻译：整体式电子包装组件
公开(公告)号：WO1996003020A1
公开(公告)日：1996-02-01
申请号：PCT/US1995008305
申请日：1995-07-03
申请人： OLIN CORPORATION
发明人： OLIN CORPORATION , MAHULIKAR, Deepak , HOFFMAN, Paul, R. , BRADEN, Jeffrey, S.
IPC分类号： H05K01/03
CPC分类号： H01L25/0657 , H01L21/4828 , H01L23/13 , H01L23/142 , H01L23/24 , H01L23/49816 , H01L24/48 , H01L24/49 , H01L25/105 , H01L2221/68377 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/49171 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/1058 , H01L2225/1076 , H01L2924/00014 , H01L2924/01012 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/16152 , H01L2924/163 , H01L2924/181 , H01L2924/3025 , H01L2224/45099 , H01L2924/00012
摘要： There is disclosed a component (61) for electronic packaging applications. A metallic substrate (62) having a centrally disposed cavity (68) is coated with an electrical isolating layer (64). Circuit traces (66) electrically interconnect a semiconductor device (54) with solder balls (70). A potting compound (60) encapsulates the integrated circuit device (54) and a portion of the circuit traces (66).
摘要翻译：公开了一种用于电子封装应用的部件（61）。具有中心设置的空腔（68）的金属基底（62）涂覆有电隔离层（64）。电路迹线（66）使半导体器件（54）与焊料球（70）电连接。封装化合物（60）封装集成电路器件（54）和电路迹线（66）的一部分。

28. 发明申请

WO2016199437A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2016199437A1
公开(公告)日：2016-12-15
申请号：PCT/JP2016/002851
申请日：2016-06-13
申请人：株式会社ソシオネクスト
发明人：山田　隆史
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/12 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16227 , H01L2224/214 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/92 , H01L2224/92133 , H01L2224/92244 , H01L2225/06513 , H01L2225/06527 , H01L2225/06548 , H01L2225/06558 , H01L2225/06586 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1434 , H01L2924/15151 , H01L2924/15153 , H01L2924/15311 , H01L2924/00
摘要：半導体装置において、第１半導体チップ（１０）は、主面に複数の端子（１１）が設けられた第１端子部（１２）を有し、裏面が支持体（１）の表面上に実装されている。第２半導体チップ（２０）は、主面に複数の端子（２１）が設けられた第２端子部（２２）を有し、主面が第１半導体チップ（１０）の主面と対向しており、第２端子部（２２）の各端子（２１）が第１端子部（１２）の各端子（１１）とそれぞれ接続されている。第１半導体チップ（１０）と半導体装置の外部端子（２）とは、単一金属からなる導体（６，７）によって接続されている。
摘要翻译：提供一种半导体器件，其中第一半导体芯片（10）在其主表面上具有设置有多个端子（11）的第一端子部（12），并且芯片的背面安装在支撑件（1）的前表面。第二半导体芯片（20）在其主表面上具有第二端子部（22），其中设置有多个端子（21），所述主表面面对第一半导体芯片（10）的主表面，并且第二端子部分（22）的端子（21）分别连接到第一端子部分（12）的端子（11）。半导体器件的第一半导体芯片（10）和外部端子（2）由包括单个金属的导体（6,7）连接。

29. 发明申请

WO2016102066A1 METHOD FOR ELECTROMAGNETIC SHIELDING AND THERMAL MANAGEMENT OF ACTIVE COMPONENTS 审中-公开
标题翻译：电磁屏蔽方法和主动元件的热管理
公开(公告)号：WO2016102066A1
公开(公告)日：2016-06-30
申请号：PCT/EP2015/002594
申请日：2015-12-22
申请人： ATOTECH DEUTSCHLAND GMBH
发明人： MUKAI, Kenichiroh , KIM, Kwonil , GAHERTY, Lee , BRANDT, Lutz , MAGAYA, Tafadzwa
IPC分类号： H01L23/552 , H01L23/31
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/3142 , H01L23/552 , H01L25/50 , H01L2225/06537 , H01L2225/06586 , H01L2225/06589 , H01L2924/15311
摘要： The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet chemical metal plating, using an adhesion promotion layer on the layer of molding compound and forming at least one metal layer on the adhesion promotion layer or forming at least one metal layer on the adhesion promotion layer by wet chemical metal plating processes.
摘要翻译：本发明涉及一种用于形成用于电磁屏蔽的金属层和有效成分的热处理的方法，优选通过湿式化学金属电镀，在模塑料层上使用粘附促进层，并在粘合促进层上形成至少一层金属层通过湿化学金属电镀工艺在粘合促进层上形成至少一层金属层。

30. 发明申请

WO2005036610A3 MULTI-SURFACE CONTACT IC PACKAGING STRUCTURES AND ASSEMBLIES 审中-公开
标题翻译：多表面接触IC封装结构和组件
公开(公告)号：WO2005036610A3
公开(公告)日：2009-04-30
申请号：PCT/US2004033778
申请日：2004-10-12
申请人： SILICON PIPE INC , OBENHUBER INESSA , FJELSTAD JOSEPH C , SEGARAM PARA K , GRUNDY KEVIN P , WIEDEMANN WILLIAM F
发明人： FJELSTAD JOSEPH C , SEGARAM PARA K , GRUNDY KEVIN P , WIEDEMANN WILLIAM F
IPC分类号： H01L23/02 , H01L20060101 , H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L23/04 , H01L23/12 , H01L23/13 , H01L23/28 , H01L23/31 , H01L23/34 , H01L23/48 , H01L23/498 , H01L23/52 , H01L25/065 , H01L29/40
CPC分类号： H01L23/13 , H01L23/3128 , H01L23/49805 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/16 , H01L2224/32145 , H01L2224/32188 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/8592 , H01L2225/0651 , H01L2225/06555 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15173 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
摘要翻译：本发明的成本有效，高性能的IC封装组件包括从IC封装组件的多个表面和电平中的任何一个上的至少一个芯片到端子的阶梯层的再分配电路。组件的关键路径电路没有电镀通孔，并且通过倒装芯片或引线键合方法将互连封装与IC芯片端子互连的互连端直接布线。

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