专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

WO2008084016A1 PROTECTION D'INFORMATIONS CONTENUES DANS UN CIRCUIT ELECTRONIQUE 审中-公开
标题翻译：保护电子电路中的信息
公开(公告)号：WO2008084016A1
公开(公告)日：2008-07-17
申请号：PCT/EP2008/050072
申请日：2008-01-04
申请人： PROTON WORLD INTERNATIONAL N.V. , MODAVE, Jean-Louis , HUQUE, Thierry
发明人： MODAVE, Jean-Louis , HUQUE, Thierry
IPC分类号： G06F21/00
CPC分类号： G07F7/082 , G04F10/10 , G06F21/75 , G06F21/755 , G06F21/77 , G06Q20/343 , G06Q20/4016 , G11C8/20 , G11C16/22 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： L'invention concerne un procédé et un circuit de protection d'informations contenues dans un circuit électronique contre une perturbation de son fonctionnement, dans lequel une détection d'une perturbation conditionne l'incrément ou le décrément (47) d'un compteur (COUNT) sur au moins un bit, le compteur étant réinitialisé automatiquement au bout d'une durée indépendante du fait que le circuit soit alimenté ou non.
摘要翻译：本发明涉及一种用于保护包含在电子电路中的信息以防止操作干扰的方法和电路，其中，在检测到干扰之后，计数器（COUNT）递增或递减（47）至少一位，所述计数器在一段时间结束时自动重新启动，独立于电路是否通电。

22. 发明申请

WO2008053472A2 READING MEMORY CELLS USING MULTIPLE THRESHOLDS 审中-公开
标题翻译：使用多个阈值读取记忆细胞
公开(公告)号：WO2008053472A2
公开(公告)日：2008-05-08
申请号：PCT/IL2007/001315
申请日：2007-10-30
申请人： ANOBIT TECHNOLOGIES LTD. , SOMMER, Naftali , SHALVI, Ofir , SOKOLOV, Dotan
发明人： SOMMER, Naftali , SHALVI, Ofir , SOKOLOV, Dotan
IPC分类号： G06F12/02 , G06F1/32 , G06F13/14 , G11C11/34
CPC分类号： G06F11/1068 , G11C8/20 , G11C11/56 , G11C11/5642 , G11C27/005
摘要： A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.
摘要翻译：一种用于操作存储器（28）的方法包括：通过将从一组标称值中选择的相应模拟输入值写入到存储器的模拟存储器单元（32）中来存储用错误校正码（ECC）编码的数据，模拟存储单元。通过执行将模拟存储器单元的模拟输出值与不同的相应读取阈值进行比较的多个读取操作来读取存储的数据，以便为每个模拟存储器单元产生多个比较结果。读取阈值中的至少两个位于在标称值的集合中彼此相邻的一对标称值之间。响应于多个比较结果计算软度量。使用软指标对ECC进行解码，以便提取存储在模拟存储单元中的数据。

23. 发明申请

WO02099809A2 METHOD AND DEVICE FOR MASKING OUT NON-SERVICEABLE MEMORY CELLS 审中-公开
标题翻译：隐藏的方法和设备无法正常运行高效的内存CELL
公开(公告)号：WO02099809A2
公开(公告)日：2002-12-12
申请号：PCT/EP0206145
申请日：2002-06-04
申请人： INFINEON TECHNOLOGIES AG , DIRSCHERL GERD , HARTLIEB HEIMO , MAY CHRISTIAN , SEDLAK HOLGER
发明人： DIRSCHERL GERD , HARTLIEB HEIMO , MAY CHRISTIAN , SEDLAK HOLGER
IPC分类号： G11C8/20
CPC分类号： G11C8/20
摘要： The invention relates to a method for controlling the mapping of a logical address of a logical address space to a physical address of a physical address space (20). Said method involves the following steps: a first physical address and a corresponding memory cell, which are associated by the mapping (30) of a logical address, are determined; the memory cell is checked for serviceability; and the mapping (30) is modified if the check reveals that the memory cell is not serviceable, in such a way that the logical address is mapped to a second physical address in the physical address space (20). In this way, access to a physical memory is carried out by means of logical addresses which are mapped to the physical addresses of the physical memory, i.e. virtual memory addressing is used in order to mask out non-serviceable memory cells in a simple and effective manner.
摘要翻译：为一个逻辑地址空间的逻辑地址的图像的用于控制到物理地址空间（20）的物理的本发明的方法包括：确定经由所述映射与逻辑地址相关联的第一物理地址和相关联的存储单元（30），检查存储器单元自己的能力发挥功能并改变所述映射（30），如果检查的步骤示出了存储单元是无功能的，因此，逻辑地址被映射到物理地址空间（20）的第二物理地址。以这种方式，通过由一个映射映射到物理存储器，即物理地址的逻辑地址的装置进行访问的物理存储器虚拟存储器寻址，用于以简单和有效的方式筛选出的非功能存储单元。

24. 发明申请

WO1997004378A1 MICROCIRCUIT WITH MEMORY THAT IS PROTECTED BY BOTH HARDWARE AND SOFTWARE 审中-公开
标题翻译：具有由两个硬件和软件保护的存储器的MICROCIRCUIT
公开(公告)号：WO1997004378A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011953
申请日：1996-07-19
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , LITTLE, Wendell, L. , CURRY, Stephen, M. , GRIDER, Steven, N. , THROWER, Mark, L. , HASS, Steven, N. , BOLAN, Michael, L. , FIESELER, Ricky, D. , HARRINGTON, Bradley, M.
IPC分类号： G06F01/00
CPC分类号： G06F7/588 , G06F9/30134 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , H04L25/026 , Y10S257/922
摘要： A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that my be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that my be produced by a prespecified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.
摘要翻译：一种安全的电子数据模块，其包含具有由硬件和软件机构的组合保护的存储器的类型的单片半导体芯片，从而防止对存储在存储器中的数据的未经授权的访问。单片半导体芯片包括用于将芯片附着到作为印刷电路板或另一芯片的基板的多个焊料凸块; 使用最小几何形状的多级隔行电源和地线; 以及检测电路块，用于检测通过未经授权的访问引起的操作状态的预先指定的变化产生的外部跳闸信号，或者可以通过短路电源和地线产生的内部跳闸信号或通过改变振荡器的频率，也与安全存储器的未授权访问相关联或附加。

25. 发明申请

WO1997004377A1 SINGLE CHIP MICROPROCESSOR, MATH CO-PROCESSOR, RANDOM NUMBER GENERATOR, REAL-TIME CLOCK AND RAM HAVING A ONE-WIRE INTERFACE 审中-公开
标题翻译：单芯片微处理器，数字处理器，随机数发生器，具有一线接口的实时时钟和RAM
公开(公告)号：WO1997004377A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011952
申请日：1996-07-19
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , LITTLE, Wendell, L. , CURIGER, Andreas
IPC分类号： G06F01/00
CPC分类号： G06F7/588 , G06F9/30134 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , H04L25/026 , Y10S257/922
摘要： A secure electronic data module containing a monolithic semiconductor chip of the type having a microprocessor, a math co-processor, a random number generator, a real-time clock, a nonvolatile data memory, a program memory, and a one-wire bus interface. The monolithic semiconductor chip is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; and a multilevel interlaced power and ground lines using minimum geometries. Large-volume data transfer over the one-wire bus between the electronic data module and a master is effectuated by using intermediate product registers in the math co-processor so that transfer time load on the microprocessor is minimized.
摘要翻译：包含具有微处理器的类型的单片半导体芯片，数学协处理器，随机数发生器，实时时钟，非易失性数据存储器，程序存储器和单线总线接口的安全电子数据模块。单片半导体芯片通过硬件和软件机制的组合来保护，从而防止对存储在存储器中的数据的未经授权的访问。单片半导体芯片包括用于将芯片附接到可以是印刷电路板或另一芯片的基板的多个焊料凸块; 以及使用最小几何形状的多层隔行电力和地线。通过在数学协处理器中使用中间产品寄存器来实现电子数据模块和主器件之间的单线总线上的大容量数据传输，从而最小化微处理器上的传输时间负载。

26. 发明申请

WO1993015508A1 ILLEGAL ADDRESS DETECTOR FOR SEMICONDUCTOR MEMORIES 审中-公开
标题翻译：用于半导体存储器的非法地址检测器
公开(公告)号：WO1993015508A1
公开(公告)日：1993-08-05
申请号：PCT/US1993000218
申请日：1993-01-14
申请人： VLSI TECHNOLOGY, INC.
发明人： VLSI TECHNOLOGY, INC. , SHIFFER, James, David, II
IPC分类号： G11C11/40
CPC分类号： G06F11/0763 , G11C8/20
摘要： When a user request a RAM or other semiconductor memory to be compiled with a number of rows that is not a power of two, the compiler creates the RAM with one extra row. The rows requested by the user are placed at contiguous row addresses starting at zero and ending at one less than the number of rows requested. The highest of these row addresses is placed permanently in a comparator (18, 20, 24, 26, 28, 30, 32 and 34) by the compiler. The comparator than compares each row address input to the RAM to the row address contained in the comparator. If the row address input is higher, then the comparator selects the exta row. The extra row can be written into or read from in the same manner as any other row in the RAM. The delay of the comparator is comparable to the delay of the address decoder, so that the RAM operates within the same specifications regardless of whether the address decoder selects a row or the comparator selects the extra row.

27. 发明申请

WO2014008211A1 EMBEDDED NON-VOLATILE MEMORY CIRCUIT FOR IMPLEMENTING LOGIC FUNCTIONS ACROSS PERIODS OF POWER DISRUPTION 审中-公开
标题翻译：用于在断电期间实施逻辑功能的嵌入式非易失性存储器电路
公开(公告)号：WO2014008211A1
公开(公告)日：2014-01-09
申请号：PCT/US2013/048982
申请日：2013-07-01
申请人： RADIANT TECHNOLOGIES, INC. , EVANS, Joseph, T.
发明人： EVANS, Joseph, T.
IPC分类号： G11C5/14 , G11C16/30
CPC分类号： G11C5/148 , G11C7/1006 , G11C7/20 , G11C7/24 , G11C8/20 , G11C11/221 , G11C14/00 , G11C16/22 , G11C19/005 , H01L27/11502 , H03K3/356008
摘要： A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts, In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.
摘要翻译：公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。当在第一和第二AML电力触点之间提供电力时，开关被定位成防止AML的状态改变。在本发明的一个方面，该电路可以包括与另一个AML输入串联的第二开关， AML输出和与AML输入或AML输出串联的锁存器。锁存器的定位使得AML输出和AML输入之间不存在直接回路。

28. 发明申请

WO2012128000A1 半導体記憶装置およびその制御方法审中-公开
标题翻译：半导体存储装置及其控制方法
公开(公告)号：WO2012128000A1
公开(公告)日：2012-09-27
申请号：PCT/JP2012/054985
申请日：2012-02-28
申请人：株式会社東芝 , 滝澤亮介
发明人：滝澤　亮介
IPC分类号： G11C11/15 , G11C11/407
CPC分类号： G06F12/0238 , G06F3/0604 , G06F3/0644 , G06F3/0688 , G06F12/00 , G06F12/1416 , G06F12/1425 , G06F12/1441 , G06F2212/1016 , G06F2212/202 , G11C7/1009 , G11C7/24 , G11C8/08 , G11C8/20 , G11C11/1695
摘要：　本実施形態に従ったメモリは、データを記憶するメモリセルアレイと、メモリセルにデータを書き込むライトドライバとを備える。ライトドライバは、書込みデータとともに入力されるライトマスクデータに従ってデータの書込みを実行し、あるいは、書込みを実行しない。マルチプレクサは、ライトマスクデータのうち書込みデータの書き込みを禁止するコマンドに固定された書込み禁止信号とライトマスクデータとのいずれかを選択的に出力する。ライトプロテクトコントローラは、書込み禁止領域のアドレスと書込みデータのアドレスとが一致する場合に書込み禁止信号をマルチプレクサに出力させ、書込み禁止領域のアドレスと書込みデータのアドレスとが一致しない場合にライトマスクデータをそのまま出力させる。
摘要翻译：根据本发明的实施例，存储器具有存储数据的存储单元阵列，以及将数据写入存储单元的写入驱动器。写入驱动器根据写入数据的写入掩码数据写入或不写入数据。复用器选择性地输出写入掩码数据或写入禁止信号，该写入禁止信号固定在写入掩码数据之中，禁止写入数据的写入的命令。当写禁止区域的地址与写入数据的地址一致时，写保护控制器使多路复用器输出写禁止信号，并且当写禁止区的地址和写入数据的地址不一致。

29. 发明申请

WO2009105203A1 METHOD AND APPARATUS FOR ACCESSING A BIDIRECTIONAL MEMORY 审中-公开
标题翻译：用于访问双向存储器的方法和装置
公开(公告)号：WO2009105203A1
公开(公告)日：2009-08-27
申请号：PCT/US2009/001016
申请日：2009-02-18
申请人： OVONYX, INC. , PARKINSON, Ward
发明人： PARKINSON, Ward
IPC分类号： G11C11/00 , G11C7/10 , G11C7/18 , G11C8/14
CPC分类号： G11C8/16 , G11C8/20 , G11C11/16 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/76
摘要： A bidirectional memory cell includes an ovonic threshold switch (OTS) and a bidirectional memory element. The OTS is configured to select the bidirectional memory element and to prevent inadvertent accesses to the memory element.
摘要翻译：双向存储器单元包括一个双极性门限开关（OTS）和双向存储元件。 OTS被配置为选择双向存储器元件并且防止对存储器元件的无意访问。

30. 发明申请

WO2008104049A1 DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION 审中-公开
标题翻译：通过页面擦除功能中的地址转换检测来解码控制
公开(公告)号：WO2008104049A1
公开(公告)日：2008-09-04
申请号：PCT/CA2008/000252
申请日：2008-02-08
申请人： MOSAID Technologies Incorporated , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C8/12 , G11C16/02 , G11C7/24 , G11C8/20
CPC分类号： G11C16/08 , G11C8/12 , G11C8/20 , G11C16/16
摘要： Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.
摘要翻译：电路和方法用于控制闪存中的多页擦除操作。多页擦除操作的每个地址的页面地址被锁存在字线解码器中。页选择复位发生器电路处理多页擦除操作的每个地址的块地址。在地址与不同块中的页面相关的情况下，先前锁存的页面地址被重置。这样可以避免在多页擦除操作中包含不同块中的多个页面时导致的不正确的电路操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式