专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008104049A1 DECODING CONTROL WITH ADDRESS TRANSITION DETECTION IN PAGE ERASE FUNCTION 审中-公开
标题翻译：通过页面擦除功能中的地址转换检测来解码控制
公开(公告)号：WO2008104049A1
公开(公告)日：2008-09-04
申请号：PCT/CA2008/000252
申请日：2008-02-08
申请人： MOSAID Technologies Incorporated , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C8/12 , G11C16/02 , G11C7/24 , G11C8/20
CPC分类号： G11C16/08 , G11C8/12 , G11C8/20 , G11C16/16
摘要： Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.
摘要翻译：电路和方法用于控制闪存中的多页擦除操作。多页擦除操作的每个地址的页面地址被锁存在字线解码器中。页选择复位发生器电路处理多页擦除操作的每个地址的块地址。在地址与不同块中的页面相关的情况下，先前锁存的页面地址被重置。这样可以避免在多页擦除操作中包含不同块中的多个页面时导致的不正确的电路操作。

2. 发明申请

WO2008067658A1 SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE 审中-公开
标题翻译：混合型记忆装置的操作系统及方法
公开(公告)号：WO2008067658A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002182
申请日：2007-12-04
申请人： MOSAID TECHNOLOGIES INCORPORATED , OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
发明人： OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
IPC分类号： G11C8/18 , G06F12/00 , G11C11/34 , G11C16/02 , G11C8/04 , G11C8/06
CPC分类号： G11C16/08 , G11C7/10 , G11C7/1078 , G11C7/20
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

3. 发明申请

WO2008067642A1 APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 审中-公开
标题翻译：用于生产混合类型的串联互连设备的设备标识符的装置和方法
公开(公告)号：WO2008067642A1
公开(公告)日：2008-06-12
申请号：PCT/CA2007/002147
申请日：2007-11-29
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , SUMI, Shuji , KIM, Jin-Ki
发明人： PYEON, Hong Beom , OH, HakJune , SUMI, Shuji , KIM, Jin-Ki
IPC分类号： G11C8/06 , G11C16/20 , G11C8/12
CPC分类号： G11C16/20 , G11C8/12
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (Sl) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a "don't care" code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。每个设备都有其设备类型的设备类型信息。包含在串行输入（S1）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。在将不同的设备类型分别提供给互连设备的情况下，在不同设备类型的每一种中生成顺序ID，并且还识别每种设备类型的总数。在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异如何。

4. 发明申请

WO2008014594A1 PULSE COUNTER WITH CLOCK EDGE RECOVERY 审中-公开
标题翻译：具有时钟边缘恢复的脉冲计数器
公开(公告)号：WO2008014594A1
公开(公告)日：2008-02-07
申请号：PCT/CA2007/001193
申请日：2007-07-06
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： H03K23/40 , H03K23/42
CPC分类号： H03K21/38
摘要： An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The clock edge recovery output signal contains a respective full clock pulse for each of either the rising or falling edge of the input pulses of the clock signal that occurs while the input gating signal is in an enable state and when the input gating signal transitions from the enable state to the disable state. A counter circuit counts the pulses contained in the clock edge recovery output signal.
摘要翻译：提供了一种用于在特定时间间隔期间对输入脉冲进行计数的装置和方法。响应于输入门控信号和包含输入脉冲的时钟信号产生时钟沿恢复输出信号。时钟沿恢复输出信号包含相应的全时钟脉冲，用于在输入门控信号处于使能状态时发生的时钟信号的输入脉冲的上升沿或下降沿中的每一个，并且当输入选通信号从使能状态为禁用状态。计数器电路对包含在时钟沿恢复输出信号中的脉冲进行计数。

5. 发明申请

WO2009079749A1 DATA STORAGE AND STACKABLE CONFIGURATIONS 审中-公开
标题翻译：数据存储和堆叠配置
公开(公告)号：WO2009079749A1
公开(公告)日：2009-07-02
申请号：PCT/CA2008/002145
申请日：2008-12-11
申请人： MOSAID TECHNOLOGIES INCORPORATED , OH, Hakjune , KIM, Jin-Ki , PYEON, Hong Beom
发明人： OH, Hakjune , KIM, Jin-Ki , PYEON, Hong Beom
IPC分类号： G11C5/06 , G11C16/02 , G11C5/02 , H01L23/48 , H01L23/52 , H01L23/535 , G11C7/10
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆叠，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出和来自堆叠中的一个存储器设备的输入之间的链接，存储器件堆可以包括通过其存储器件便于一个或多个串联连接配置的路径。

6. 发明申请

WO2008134858A1 MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION 审中-公开
标题翻译：具有双重功能的多级电池访问缓冲器
公开(公告)号：WO2008134858A1
公开(公告)日：2008-11-13
申请号：PCT/CA2008/000797
申请日：2008-04-28
申请人： MOSAID Technologies Incorporated , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C7/10 , G11C11/40 , G11C11/41 , G11C11/413 , G11C16/02 , G11C7/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5642 , G11C2211/5647
摘要： An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.
摘要翻译：提供了使用两级MLC（多级单元）操作的诸如页面缓冲器的访问缓冲器，用于写入诸如Flash的非易失性存储器。访问缓冲器具有用于临时存储要写入的数据的第一锁存器。提供第二锁存器用于从作为两级写入操作的一部分的数据从存储器读取数据。第二个锁存器具有从存储器读取时参与锁存功能的反相器。相同的反相器用于产生正被写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。

7. 发明申请

WO2008098349A1 SEMICONDUCTOR DEVICE AND METHOD FOR SELECTION AND DE-SELECTION OF MEMORY DEVICES INTERCONNECTED IN SERIES 审中-公开
标题翻译：用于选择和选择系列中互连的存储器件的半导体器件和方法
公开(公告)号：WO2008098349A1
公开(公告)日：2008-08-21
申请号：PCT/CA2008/000219
申请日：2008-02-05
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C8/18 , G06F1/04 , G11C11/34 , G11C19/00 , G11C8/12
CPC分类号： G11C19/00
摘要： A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.
摘要翻译：系统包括与存储器控制器通信的串联连接的多个存储器件。当存储器装置接收到指示具有ID号的命令的开始的命令选通信号时，将存储器件置于取消选择状态，并将ID号与存储器件的器件地址进行比较。当存储器件处于取消选择状态时，命令选通信号和命令的延迟版本被转发。如果ID编号与设备地址相匹配，则将存储设备置于选择状态。在选择状态下，存储装置可以避免转发命令选通信号和命令的延迟版本，使得如果存在匹配，则在将存储装置置于选择状态之前转发命令的截断部分。

8. 发明申请

WO2008070978A1 MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES 审中-公开
标题翻译：具有串行和并行模式的记忆系统和方法
公开(公告)号：WO2008070978A1
公开(公告)日：2008-06-19
申请号：PCT/CA2007/002222
申请日：2007-12-10
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C11/34 , H03M9/00
CPC分类号： G11C7/1045 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C2207/107
摘要： Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.
摘要翻译：提供了允许使用串行访问或使用并行访问来执行访问一个或多个存储体的方法和系统。在串行模式下，每个链路都作为一个独立的串行链路运行。相比之下，在串行模式下，链路作为并行链路共同工作。在为串行模式的每个链路独立接收输入和输出控制的情况下，在并行模式期间，所有链路都使用一组输入和输出控制。

9. 发明申请

WO2008037064A1 PACKET BASED ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
标题翻译：用于串行互连设备的基于分组的ID生成
公开(公告)号：WO2008037064A1
公开(公告)日：2008-04-03
申请号：PCT/CA2007/001661
申请日：2007-09-18
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , OH, HakJune
发明人： PYEON, Hong Beom , OH, HakJune
IPC分类号： G06F13/00 , G06F1/04 , H03K5/14
CPC分类号： G06F1/12 , G06F1/04 , G11C5/00 , G11C5/066 , G11C7/20
摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
摘要翻译：各种存储器件（例如，DRAM，闪存）串联连接。存储器件需要它们的标识符（ID）。每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。命令数据和先前生成的ID数据被同步地注册。注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。计算是一个加法或减法。通过解释响应于时钟在串行输入处接收的基于串行数据包的命令，以分组的形式生成ID。响应于解释的ID和时钟来控制时钟延迟。根据受控时钟延迟，以分组为基础提供新的ID。在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

10. 发明申请

WO2007124558A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF- REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF- REFRESH 审中-公开
标题翻译：动态随机访问存储器件及其自动补偿存储器单元的温度补偿自刷新方法
公开(公告)号：WO2007124558A1
公开(公告)日：2007-11-08
申请号：PCT/CA2007/000529
申请日：2007-03-30
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self- refresh for variable DRAM cell retention time.
摘要翻译：动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。阵列的每个DRAM单元与相应列的相应行和位线的字线相连。通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。响应于自刷新模式信号产生的振荡电路产生基本时间段。第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。在自刷新模式下，存储在DRAM单元中的数据被刷新。根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式