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1. 发明申请

WO1990010983A1 TELECOMMUNICATIONS INTERFACE WITH IMPROVED JITTER REPORTING 审中-公开
标题翻译：电信接口与改进的智能手机报告
公开(公告)号：WO1990010983A1
公开(公告)日：1990-09-20
申请号：PCT/US1990001436
申请日：1990-03-16
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , WHITESIDE, Frank, A. , SMITH, Michael, D.
IPC分类号： H04L07/027
CPC分类号： H04J3/0626
摘要： A communications receiver, wherein an elastic store FIFO (200) buffers clock-phase jitter. A jitter estimate (203') is obtained by a very simple circuit, wherein the read clock is used as a reference to sample the FIFO address pointers (305, 309).

2. 发明申请

WO1990006633A1 MICROPOWERED RF DATA MODULES 审中-公开
标题翻译：微波RF数据模块
公开(公告)号：WO1990006633A1
公开(公告)日：1990-06-14
申请号：PCT/US1989005579
申请日：1989-12-08
申请人： DALLAS SEMICONDUCTOR CORPORATION , LEE, Robert, D. , DIAS, Donald, R. , MOUNGER, Robert, W. , BOLAN, Michael, L. , HEPTIG, John, Patrick , KURKOWSKI, Hal , KLUGHART, Kevin, M.
发明人： DALLAS SEMICONDUCTOR CORPORATION
IPC分类号： H04B01/00
CPC分类号： H04W52/0216 , H04B1/403 , H04W52/0229 , Y02D70/122 , Y02D70/26 , Y02D70/40
摘要： A low-power wireless data communication system, in which base stations (110) can automatically interface to batter-powered portable data modules (210) as they are brought within range. In the data modules (210), each receive antenna (121) is directly connected to a gain-controlled comparator (420A, 420B). Bandpass filtering (448) is accomplished economically by use of simple digital circuits. The two-level digital output from the comparator (420A, 420B) is fed (through an intersymbol detector, a counter, and a ripple-through magnitude comparator) to a state machine (552), which decodes the resulting digital waveform to a conventional serial-bus format. The internal data bus (701D) provides an interface to memory chips (262) and (optionally) to other chips, such as an electronic key. The decoder chip (220) also provides a secondary power supply to the other chips (230), and modulates the power supply (250) to assist detection of transitions on the reset-bar line of the serial bus (206). The modules (230) use widely different frequencies for read and write operations. (Transmissions by the base station (110) use a pulse-width modulation scheme where the most commonly used signals correspond to the shortest pulse. A "read" command is encoded as the same pulse width as one of the two write commands). In addition, a pair of touch contacts (270) can be used to override the RF link. Error-checking (Fig. 7E) is performed on incoming commands before memory access (260) is permitted. "Freshness seal" logic (510) prevents any battery drain until the module is initially turned on (by placing it in a strong field).
摘要翻译：一种低功率无线数据通信系统，其中基站（110）在其被带入范围内时可以自动地与电池供电的便携式数据模块（210）接口。在数据模块（210）中，每个接收天线（121）直接连接到增益控制比较器（420A，420B）。带通滤波（448）通过简单的数字电路经济实现。来自比较器（420A，420B）的两级数字输出（通过符号间检测器，计数器和纹波幅度比较器）馈送到状态机（552），其将所得数字波形解码为常规串行总线格式。内部数据总线（701D）提供到存储器芯片（262）和（可选地）到诸如电子钥匙的其他芯片的接口。解码器芯片（220）还向其他芯片（230）提供次级电源，并且调制电源（250）以辅助检测串行总线（206）的复位线上的转换。模块（230）对于读取和写入操作使用广泛不同的频率。（基站（110）的传输使用脉冲宽度调制方案，其中最常用的信号对应于最短脉冲，“读取”命令被编码为与两个写命令之一相同的脉冲宽度）。此外，可以使用一对触摸触点（270）来覆盖RF链路。在允许存储器访问（260）之前对输入命令执行错误检查（图7E）。 “新鲜密封”逻辑（510）防止任何电池耗尽，直到模块最初打开（通过将其放在强场中）。

3. 发明申请

WO1990006548A1 TELEPHONE-PROGRAMMABLE COMPUTER 审中-公开
标题翻译：电话可编程计算机
公开(公告)号：WO1990006548A1
公开(公告)日：1990-06-14
申请号：PCT/US1989005457
申请日：1989-11-30
申请人： DALLAS SEMICONDUCTOR CORPORATION , GRIDER, Stephen, N. , FOLKES, Don , CURRY, Stephen, M. , LITTLE, Wendell, L.
发明人： DALLAS SEMICONDUCTOR CORPORATION
IPC分类号： G06F03/00
CPC分类号： G06F11/2294 , G06F8/65 , G06F11/20 , G06F11/3656 , H04L29/06 , H04M11/00
摘要： A computer system is provided which can be completely reprogrammed by telephone to permit debugging or software updating. Since low-level access is possible, this system can be used for data-collection stations, for application-specific systems generally, or for other systems in which a high-level software environment is not present. The present computer system can be used with major home appliances such as washing machines, dryers, microwave ovens which contain microcontrollers. The computer system comprises first and second microcontrollers (110, 120). The first or target microcontroller (110) further includes memory (112) and clock/calendar (114). Second microcontroller (120) includes control logic (120A) and a modem controller (120B). The USART (130) is used for serial data transfers from the target microcontroller (110) when communication is established over the telephone lines.
摘要翻译：提供了可以通过电话完全重新编程以允许调试或软件更新的计算机系统。由于可以进行低级访问，因此该系统可以用于数据采集站，一般用于特定于应用程序的系统，也可用于不存在高级别软件环境的其他系统。本计算机系统可以与诸如洗衣机，干衣机，微波炉等主要家用电器一起使用。计算机系统包括第一和第二微控制器（110,120）。第一或目标微控制器（110）还包括存储器（112）和时钟/日历（114）。第二微控制器（120）包括控制逻辑（120A）和调制解调器控制器（120B）。当通过电话线建立通信时，USART（130）用于从目标微控制器（110）的串行数据传输。

4. 发明申请

WO1997004378A1 MICROCIRCUIT WITH MEMORY THAT IS PROTECTED BY BOTH HARDWARE AND SOFTWARE 审中-公开
标题翻译：具有由两个硬件和软件保护的存储器的MICROCIRCUIT
公开(公告)号：WO1997004378A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011953
申请日：1996-07-19
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , LITTLE, Wendell, L. , CURRY, Stephen, M. , GRIDER, Steven, N. , THROWER, Mark, L. , HASS, Steven, N. , BOLAN, Michael, L. , FIESELER, Ricky, D. , HARRINGTON, Bradley, M.
IPC分类号： G06F01/00
CPC分类号： G06F7/588 , G06F9/30134 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , H04L25/026 , Y10S257/922
摘要： A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that my be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that my be produced by a prespecified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.
摘要翻译：一种安全的电子数据模块，其包含具有由硬件和软件机构的组合保护的存储器的类型的单片半导体芯片，从而防止对存储在存储器中的数据的未经授权的访问。单片半导体芯片包括用于将芯片附着到作为印刷电路板或另一芯片的基板的多个焊料凸块; 使用最小几何形状的多级隔行电源和地线; 以及检测电路块，用于检测通过未经授权的访问引起的操作状态的预先指定的变化产生的外部跳闸信号，或者可以通过短路电源和地线产生的内部跳闸信号或通过改变振荡器的频率，也与安全存储器的未授权访问相关联或附加。

5. 发明申请

WO1997004377A1 SINGLE CHIP MICROPROCESSOR, MATH CO-PROCESSOR, RANDOM NUMBER GENERATOR, REAL-TIME CLOCK AND RAM HAVING A ONE-WIRE INTERFACE 审中-公开
标题翻译：单芯片微处理器，数字处理器，随机数发生器，具有一线接口的实时时钟和RAM
公开(公告)号：WO1997004377A1
公开(公告)日：1997-02-06
申请号：PCT/US1996011952
申请日：1996-07-19
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , LITTLE, Wendell, L. , CURIGER, Andreas
IPC分类号： G06F01/00
CPC分类号： G06F7/588 , G06F9/30134 , G06F11/1004 , G06F21/602 , G06F21/72 , G06F21/73 , G06F21/75 , G06F21/81 , G06F21/86 , G06F21/87 , G06F2211/007 , G06F2221/2143 , G06F2221/2153 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1008 , G11C5/06 , G11C5/143 , G11C7/24 , G11C8/20 , H01L23/57 , H01L2224/16225 , H01L2924/16152 , H01L2924/3011 , H04L25/026 , Y10S257/922
摘要： A secure electronic data module containing a monolithic semiconductor chip of the type having a microprocessor, a math co-processor, a random number generator, a real-time clock, a nonvolatile data memory, a program memory, and a one-wire bus interface. The monolithic semiconductor chip is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; and a multilevel interlaced power and ground lines using minimum geometries. Large-volume data transfer over the one-wire bus between the electronic data module and a master is effectuated by using intermediate product registers in the math co-processor so that transfer time load on the microprocessor is minimized.
摘要翻译：包含具有微处理器的类型的单片半导体芯片，数学协处理器，随机数发生器，实时时钟，非易失性数据存储器，程序存储器和单线总线接口的安全电子数据模块。单片半导体芯片通过硬件和软件机制的组合来保护，从而防止对存储在存储器中的数据的未经授权的访问。单片半导体芯片包括用于将芯片附接到可以是印刷电路板或另一芯片的基板的多个焊料凸块; 以及使用最小几何形状的多层隔行电力和地线。通过在数学协处理器中使用中间产品寄存器来实现电子数据模块和主器件之间的单线总线上的大容量数据传输，从而最小化微处理器上的传输时间负载。

6. 发明申请

WO1990012401A1 MEMORY WITH POWER SUPPLY INTERCEPT AND REDUNDANCY LOGIC 审中-公开
标题翻译：具有电源干扰和冗余逻辑的存储器
公开(公告)号：WO1990012401A1
公开(公告)日：1990-10-18
申请号：PCT/US1990001987
申请日：1990-04-12
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , KURKOWSKI, Hal
IPC分类号： G11C07/00
CPC分类号： G11C29/83 , G11C29/832
摘要： A low-power SRAM with redundant rows and columns. Power supply disconnect fuses (300) permit the VDD supply voltage line for the bad row to be disconnected. Additional disconnect fuses (214) (shown in Figure 2a) permit power to be disconnected from any bitline pair in which a memory cell causes excess leakage.
摘要翻译：具有冗余行和列的低功耗SRAM。电源断开保险丝（300）允许断开不良行的VDD电源线。额外的断开熔断器（214）（如图2a所示）允许断电与存储器单元引起过量泄漏的任何位线对。

7. 发明申请

WO1997012344A2 METHOD, APPARATUS, SYSTEM AND FIRMWARE FOR SECURE TRANSACTIONS 审中-公开
标题翻译：方法，设备，安全交易的系统和固件
公开(公告)号：WO1997012344A2
公开(公告)日：1997-04-03
申请号：PCT/US1996015471
申请日：1996-09-26
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , CURRY, Stephen, M. , LOOMIS, Donald, W. , FOX, Christopher, W.
IPC分类号： G07F07/10
CPC分类号： G06Q20/341 , G06Q20/367 , G06Q20/3823 , G06Q20/401 , G06Q20/4093 , G06Q20/40975 , G07F7/0826 , G07F7/1008 , G07F7/1016 , H04L9/3263 , H04L9/3297 , H04L2209/34 , H04L2209/56
摘要： The present invention relates to an electronic module used for secure transactions. More specifically, the electronic module is capable of passing information back and forth between a service provider's equipment via a secure, encrypted technique so that money and other valuable data can be securely passed electronically. The module is capable of being programmed, keeping track of real time, recording transactions for later review, and creating encryption key pairs.
摘要翻译：本发明涉及一种用于安全交易的电子模块。更具体地，电子模块能够通过安全的加密技术在服务提供商的设备之间来回传递信息，从而可以通过电子方式可靠地传递货币和其他有价值的数据。该模块能够被编程，跟踪实时，记录事务以供以后审查，并创建加密密钥对。

8. 发明申请

WO1997004414A2 AN ELECTRONIC MICRO IDENTIFICATION CIRCUIT THAT IS INHERENTLY BONDED TO A SOMEONE OR SOMETHING 审中-公开
标题翻译：一个电子微型识别电路，被固定在一个或者几个
公开(公告)号：WO1997004414A2
公开(公告)日：1997-02-06
申请号：PCT/US1996011882
申请日：1996-07-19
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , BOLAN, Michael, L. , FEKETE, Nicholas
IPC分类号： G06K19/073
CPC分类号： G06K19/07758 , G06K19/073 , G06Q20/341 , G06Q20/4014 , G06Q20/40145 , G07C9/00039 , G07C9/00071 , G07C9/00111 , G07F7/1008 , G07F7/1083
摘要： This invention relates to a small portable microprocessor based circuit (electronic module) that contains information about the user of the circuit that is known or inherently known by the user. The circuit is small enough to fit inside a thickened U.S. nickel and enables a user to perform secure transactions such as money transfers, information transfers, access control, etc. The electronic module is designed to be extremely secure both physically and electronically. Furthermore, the electronic module is useless to a person other than the designated user.
摘要翻译：本发明涉及一种小型的基于便携式微处理器的电路（电子模块），其包含关于用户已知或固有地已知的电路的用户的信息。该电路足够小以适应加厚的美国镍，并使用户能够执行安全的交易，例如汇款，信息传输，访问控制等。电子模块被设计为在物理和电子方面都非常安全。此外，电子模块对于指定用户以外的人是无用的。

9. 发明申请

WO1991011007A2 SERIAL DRAM CONTROLLER WITH TRANSPARENT REFRESH 审中-公开
标题翻译：串行DRAM控制器与透明刷新
公开(公告)号：WO1991011007A2
公开(公告)日：1991-07-25
申请号：PCT/US1991000448
申请日：1991-01-22
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , AMIN, Pravin, T.
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： A DRAM controller which provides serial access to a bank of DRAMs, with totally transparent refresh control. Each falling edge of the clock line (in the serial interface) is followed by a refresh cycle, and every rising edge of CLK is followed by an active cycle. Since the clock cycles are allowed to have variable duration, a rising edge may not be followed immediately by a falling edge, and a falling edge may not be followed immediately by a rising edge. To prevent sensitivity to such variable clock circumstances, any falling edge which is not immediately followed by a rising edge will permit multiple refresh cycles to occur. Similarly, any rising edge after which the clock line remains high for more than one clock period will initially be followed by an active cycle, which is then followed by one or more refresh cycles, until the clock line goes low and then goes high again. To accomplish these timing relationships, some pipelining functionality is included in hardware.
摘要翻译： DRAM控制器，提供对一组DRAM的串行访问，具有完全透明的刷新控制。时钟线的每个下降沿（在串行接口中）之后是刷新周期，CLK的每个上升沿都跟随有效周期。由于允许时钟周期具有可变的持续时间，所以上升沿可能不会立即跟随下降沿，并且下降沿可能不会立即被上升沿跟随。为了防止对这种可变时钟环境的敏感性，任何不紧随着上升沿的下降沿将允许发生多个刷新周期。类似地，在多于一个时钟周期之后的时钟线保持高电平的任何上升沿将首先跟随有效周期，之后是一个或多个刷新周期，直到时钟线变低，然后再次变高。为了完成这些时序关系，硬件中包含一些流水线功能。

10. 发明申请

WO1991000648A1 WAVESHAPING SUBSYSTEM USING CONVERTER AND DELAY LINES 审中-公开
标题翻译：使用转换器和延迟线来波形子系统
公开(公告)号：WO1991000648A1
公开(公告)日：1991-01-10
申请号：PCT/US1990003699
申请日：1990-06-26
申请人： DALLAS SEMICONDUCTOR CORPORATION
发明人： DALLAS SEMICONDUCTOR CORPORATION , SMITH, Michael, D.
IPC分类号： H03K05/01
CPC分类号： H04L25/0286 , G06J1/00 , H04L25/0272 , H04L25/0278 , H04L25/03834
摘要： A waveform generating circuit, wherein a master clock signal is fed into a tapped string of adjustable delay lines, (810A-810G in Fig. 8) and the tapped delay outputs are used to control selection of scaled voltage fractions for output. The use of adjustable delay lines (810A-810G in Fig. 8) means that very high-domain resolution can be achieved, simply by making a small adjustment to the value of a trimmable capacitor. This structure provides a programmable time/voltage array (100 in Fig. 1), and the programming of this array determines which of the possible reference voltages will be enabled by which of the control inputs. Another set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determine which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates so that the polarity of a bipolar output can be reversed. This structure is advantageously applied to a novel digital to analog converter.
摘要翻译：一种波形发生电路，其中主时钟信号被馈送到可调延迟线的抽头串（图8中的810A-810G），并且抽头延迟输出用于控制用于输出的标定电压分数的选择。使用可调延迟线（图8中的810A-810G）意味着可以简单地通过对可调电容器的值进行小的调整来实现非常高的域分辨率。该结构提供可编程时间/电压阵列（图1中为100），并且该阵列的编程确定哪些可能的参考电压将由哪个控制输入使能。在输出连接矩阵中的另一组可编程选项可以确定哪些内部电压线将连接到哪条输出线。在输出连接矩阵之后，输出选择逻辑用于确定要使用哪一类输出电平。输出选择逻辑还优选地包括极性反转门，使得双极性输出的极性可以反转。该结构有利地应用于新颖的数模转换器。

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