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21. 发明申请

WO2016099718A1 APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：使用隧道场效应晶体管的DENSE电路的装置，方法和系统
公开(公告)号：WO2016099718A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/060180
申请日：2015-11-11
申请人： INTEL CORPORATION
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
IPC分类号： H03K19/0185
CPC分类号： G11C11/419 , G11C5/145 , G11C11/412 , H01L27/1104 , H03K3/356104
摘要： Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.
摘要翻译：实施例包括用于移位电压电平的电路的装置，方法和系统。电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。还描述了低电压存储器阵列。在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列和高电压域的逻辑分量的逻辑组件之间的通信。还可以描述另外的实施例。

22. 发明申请

WO2014004049A1 ISOLATED AND BULK SEMICONDUCTOR DEVICES FORMED ON A SAME BULK SUBSTRATE 审中-公开
标题翻译：在相同的大块基板上形成的隔离和大块半导体器件
公开(公告)号：WO2014004049A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/044794
申请日：2013-06-07
申请人： INTEL CORPORATION
发明人： CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , GOMEZ, Harry
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76237 , H01L21/76232 , H01L27/088 , H01L27/1207 , H01L29/0638 , H01L29/0653 , H01L29/7851
摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
摘要翻译：描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。第一半导体本体具有带有第一水平面的最上表面。半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。隔离基座设置在主体基板上。第二半导体本体具有带有第二水平面的最上表面。第一和第二水平面是共面的。

23. 发明申请

WO2013095645A1 SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS 审中-公开
标题翻译：具有调制纳米级数的半导体器件
公开(公告)号：WO2013095645A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067223
申请日：2011-12-23
申请人： INTEL CORPORATION , CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , BHIMARASETTI, Gopinath , GHANI, Tahir , KIM, Seiyon
发明人： CAPPELLANI, Annalisa , KUHN, Kelin J. , RIOS, Rafael , BHIMARASETTI, Gopinath , GHANI, Tahir , KIM, Seiyon
IPC分类号： H01L21/336 , H01L29/78 , B82B3/00
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02587 , H01L29/0673 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
摘要翻译：描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。第二半导体器件包括比第一半导体器件少的一个或多个纳米线。第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

24. 发明申请

WO2013095349A1 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS 审中-公开
标题翻译：具有金属源和漏区的半导体器件
公开(公告)号：WO2013095349A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/065931
申请日：2011-12-19
申请人： INTEL CORPORATION , GILES, Martin, D. , CAPPELLANI, Annalisa , KABEHIE, Sanaz , RIOS, Rafael , WEBER, Cory, E. , BUDREVICH, Aaron A.
发明人： GILES, Martin, D. , CAPPELLANI, Annalisa , KABEHIE, Sanaz , RIOS, Rafael , WEBER, Cory, E. , BUDREVICH, Aaron A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823814 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

25. 发明申请

WO2012074872A2 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 审中-公开
标题翻译：硅和硅纳米线的纳米结构
公开(公告)号：WO2012074872A2
公开(公告)日：2012-06-07
申请号：PCT/US2011/062059
申请日：2011-11-23
申请人： INTEL CORPORATION , KUHN, Kelin J. , KIM, Seiyon , RIOS, Rafael , CEA, Stephen M. , GILES, Martin D. , CAPPELLANI, Annalisa , RAKSHIT, Titash , CHANG, Peter , RACHMADY, Willy
发明人： KUHN, Kelin J. , KIM, Seiyon , RIOS, Rafael , CEA, Stephen M. , GILES, Martin D. , CAPPELLANI, Annalisa , RAKSHIT, Titash , CHANG, Peter , RACHMADY, Willy
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述了形成微电子结构的方法。那些方法的实施例包括形成包括衬底的纳米线器件，所述衬底包括与间隔物相邻的源极/漏极结构以及设置在间隔物之间的纳米线沟道结构，其中纳米线沟道结构垂直堆叠在彼此之上。

26. 发明申请

WO2018063343A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING BI-LAYER SEMICONDUCTING OXIDES IN SOURCE AND DRAIN FOR LOW ACCESS AND CONTACT RESISTANCE OF THIN FILM TRANSISTORS 审中-公开
标题翻译：用于实现薄膜晶体管的低接入和接触电阻的双层半导体氧化物在源极和漏极中的系统，方法和设备
公开(公告)号：WO2018063343A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054841
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , LE, Van H. , RIOS, Rafael , SHIVARAMAN, Shriram , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/78 , H01L21/768
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于在用于薄膜晶体管的低访问和接触电阻的源极/漏极中实现双层半导体氧化物的系统，方法和设备。例如，根据一个实施例公开了一种其中具有衬底的半导体器件; 由第一氧化物材料和第二氧化物材料形成的双层氧化物层，所述第一氧化物材料包含半导体氧化物材料且具有与包含高迁移率氧化物材料的所述第二氧化物材料不同的材料特性; 在衬底上形成的沟道层，沟道层由双层氧化物层的半导体氧化物材料形成; 在所述沟道层顶上形成的高迁移率氧化物层，所述高导电率氧化物层由所述双层氧化物层的高迁移率氧化物材料形成; 形成在高迁移率氧化物层顶上的金属触点; 在所述高迁移率氧化物层顶上形成的栅极氧化物材料和栅极氧化物材料，所述栅极氧化物材料与所述高迁移率氧化物层直接接触; 以及将金属触点与栅极和栅极氧化物材料分开的间隔件。披露了其他相关的实施例。

27. 发明申请

WO2018057012A1 THRESHOLD SWITCHING SELECTOR BASED MEMORY 审中-公开
标题翻译：基于阈值切换选择器的内存
公开(公告)号：WO2018057012A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053585
申请日：2016-09-23
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , LE, Van H. , DEWEY, Gilbert , RIOS, Rafael , KAVALIEROS, Jack T. , SHIVARAMAN, Shriram
IPC分类号： H01L45/00
CPC分类号： H01L27/2427 , H01L45/04 , H01L45/1233 , H01L45/14
摘要： Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell.
摘要翻译：实施例包括阈值切换选择器。阈值切换选择器可以包括阈值切换层和两个电极之间的半导体层。存储器单元可以包括耦合到存储单元的阈值切换选择器。存储单元可以是PCRAM存储单元，MRAM存储单元或RRAM存储单元。此外，RRAM器件可以包括耦合到阈值切换选择器的RRAM存储单元，其中阈值切换选择器可以包括阈值切换层和半导体层，并且阈值切换选择器的半导体层可以与 RRAM存储单元的半导体层。

28. 发明申请

WO2018044330A1 SEMICONDUCTOR MATERIAL FOR RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：半导体材料用于阻性随机存取存储器
公开(公告)号：WO2018044330A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/050289
申请日：2016-09-02
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , LE, Van H. , DEWEY, Gilbert , RIOS, Rafael , KAVALIEROS, Jack T. , SHIVARAMAN, Shriram
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/08 , H01L45/14
摘要： Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.
摘要翻译：实施例包括电阻式随机存取存储器（RRAM）存储单元，其具有电阻转换材料层和在两个电极之间的半导体层，其中半导体层用作OEL。另外，RRAM存储单元可以与晶体管耦合以形成RRAM存储器单元。 RRAM存储器单元可以包括作为晶体管的沟道的半导体层，并且还与存储单元共享为存储单元的OEL。共享电极可以用作晶体管的源电极和存储单元的电极。在一些实施例中，可以在晶体管和存储单元之间共享电介质层，其中电介质层是存储单元的电阻切换材料层。

29. 发明申请

WO2018004663A1 TWO TRANSISTOR MEMORY CELL WITH METAL OXIDE SEMICONDUCTORS AND SILICON TRANSISTORS 审中-公开
标题翻译：两个金属氧化物半导体和硅晶体管的晶体管存储器
公开(公告)号：WO2018004663A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040742
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LE, Van H. , DEWEY, Gilbert William , RIOS, Rafael , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko , SHIVARAMAN, Shriram , METERELLIYOZ, Mesut
IPC分类号： H01L27/115 , G11C16/04
摘要： A two transistor memory cell is described with amorphous oxide semiconductors and silicon transistors. In some examples a memory cell includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.
摘要翻译：用无定形氧化物半导体和硅晶体管来描述双晶体管存储器单元。在一些示例中，存储器单元包括感测晶体管，该感测晶体管具有耦合到读取位线的源极和耦合到读取字线的漏极，充电晶体管具有位于第一金属层中的源极和漏极以及位于源极和漏极之间的栅极所述漏极，其中所述栅极具有在所述源极和所述漏极之间并且耦合到所述源极和所述漏极的沟道，所述沟道由金属氧化物半导体形成，其中所述充电晶体管的源极耦合到所述感测晶体管的栅极，并且栅极电极位于耦合到充电晶体管的栅极的第二金属层。

30. 发明申请

WO2018004629A1 INTEGRATED CIRCUIT DIE HAVING BACK-END-OF-LINE TRANSISTORS 审中-公开
标题翻译：集成电路裸片具有后端线晶体管
公开(公告)号：WO2018004629A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040558
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： LE, Van Hoang , DEWEY, Gilbert William , RADOSAVLJEVIC, Marko , RIOS, Rafael , KAVALIEROS, Jack T.
IPC分类号： H01L29/66 , H01L29/78 , H01L23/29
摘要： Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of- line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.
摘要翻译：描述了具有内置在管芯的后端部分中的多栅非平面晶体管的集成电路管芯。在一个示例中，非平面晶体管包括在源模块和漏极模块之间延伸的非晶氧化物半导体（AOS）沟道。门模块可以围绕AOS通道延伸以控制源模块和排出模块之间的电流。 AOS通道可以包括具有铟镓锌氧化物的AOS层。

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